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EPF8452ATC100-4 PDF预览

EPF8452ATC100-4

更新时间: 2024-02-03 21:47:59
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件
页数 文件大小 规格书
62页 957K
描述
Programmable Logic Device Family

EPF8452ATC100-4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:LFQFP, TQFP100,.63SQReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.19Is Samacsys:N
其他特性:336 LOGIC ELEMENTSJESD-30 代码:S-PQFP-G100
JESD-609代码:e3长度:14 mm
湿度敏感等级:3专用输入次数:4
I/O 线路数量:78输入次数:68
逻辑单元数量:336输出次数:68
端子数量:100最高工作温度:70 °C
最低工作温度:组织:4 DEDICATED INPUTS, 78 I/O
输出函数:REGISTERED封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:TQFP100,.63SQ
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3.3,3.3/5,5 V
可编程逻辑类型:LOADABLE PLD认证状态:Not Qualified
座面最大高度:1.27 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

EPF8452ATC100-4 数据手册

 浏览型号EPF8452ATC100-4的Datasheet PDF文件第56页浏览型号EPF8452ATC100-4的Datasheet PDF文件第57页浏览型号EPF8452ATC100-4的Datasheet PDF文件第58页浏览型号EPF8452ATC100-4的Datasheet PDF文件第59页浏览型号EPF8452ATC100-4的Datasheet PDF文件第60页浏览型号EPF8452ATC100-4的Datasheet PDF文件第61页 
FLEX 8000 Programmable Logic Device Family Data Sheet  
Notes to tables:  
(1) Perform a complete thermal analysis before committing a design to this device package. See Application Note 74  
(Evaluating Power for Altera Devices) for more information.  
(2) This pin is a dedicated pin and is not available as a user I/O pin.  
(3) SDOUTwill drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the  
MAX+PLUS II software will not use SDOUTas a user I/O pin; the user can override the MAX+PLUS II software and  
use SDOUTas a user I/O pin.  
(4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin.  
(5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins.  
(6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration.  
(7) TRSTis a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used.  
(8) Pin 52 is a V pin on EPF8452A devices only.  
CC  
(9) The user I/O pin count includes dedicated input pins and all I/O pins.  
(10) Unused dedicated inputs should be tied to ground on the board.  
(11) SDOUTdoes not exist in the EPF8636GC192 device.  
(12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices.  
(13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins.  
(14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is  
not used, TDI, TCK, TMS, and TRSTshould be tied to GND.  
The information contained in the FLEX 8000 Programmable Logic Device  
Family Data Sheet version 11.1 supersedes information published in  
previous versions. The FLEX 8000 Programmable Logic Device Family Data  
Sheet version 11.1 contains the following change: minor textual updates.  
Revision  
History  
62  
Altera Corporation  

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