FLEX 8000
Programmable Logic
Device Family
®
January 2003, ver. 11.1
Data Sheet
1
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Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
Features...
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2,500 to 16,000 usable gates
282 to 1,500 registers
System-level features
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In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
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Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
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Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
MultiVoltTM I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
Low power consumption (typical specification is 0.5 mA or less in
standby mode)
3
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Flexible interconnect
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FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
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Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
Tri-state emulation that implements internal tri-state nets
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Powerful I/O pins
Programmable output slew-rate control reduces switching noise
Table 1. FLEX 8000 Device Features
Feature
EPF8282A
EPF8282AV
EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
Usable gates
2,500
282
26
4,000
452
42
6,000
636
63
8,000
820
84
12,000
1,188
126
16,000
1,500
162
Flipflops
Logic array blocks (LABs)
Logic elements (LEs)
Maximum user I/O pins
208
78
336
120
504
136
672
152
1,008
184
1,296
208
Altera Corporation
1
DS-F8000-11.1