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EPF10K200SRC240-1N PDF预览

EPF10K200SRC240-1N

更新时间: 2024-02-22 19:26:35
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑
页数 文件大小 规格书
110页 1604K
描述
Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240

EPF10K200SRC240-1N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:FQFP, HQFP240,1.37SQ,20针数:240
Reach Compliance Code:compliantECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.1
JESD-30 代码:S-PQFP-G240JESD-609代码:e3
长度:32 mm湿度敏感等级:3
I/O 线路数量:182输入次数:182
逻辑单元数量:9984输出次数:182
端子数量:240最高工作温度:70 °C
最低工作温度:组织:182 I/O
输出函数:MIXED封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装等效代码:HQFP240,1.37SQ,20
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):245电源:2.5,2.5/3.3 V
可编程逻辑类型:LOADABLE PLD传播延迟:0.3 ns
认证状态:Not Qualified座面最大高度:4.1 mm
子类别:Field Programmable Gate Arrays最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN (472) OVER COPPER
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:32 mmBase Number Matches:1

EPF10K200SRC240-1N 数据手册

 浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第1页浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第2页浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第4页浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第5页浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第6页浏览型号EPF10K200SRC240-1N的Datasheet PDF文件第7页 
FLEX 10KE Embedded Programmable Logic Devices Data Sheet  
Software design support and automatic place-and-route provided by  
Alteras development systems for Windows-based PCs and Sun  
SPARCstation, and HP 9000 Series 700/ 800  
Flexible package options  
Available in a variety of packages with 144 to 672 pins, including  
the innovative FineLine BGATM packages (see Tables 3 and 4)  
SameFrameTM pin-out compatibility between FLEX 10KA and  
FLEX 10KE devices across a range of device densities and pin  
counts  
Additional design entry and simulation support provided by EDIF  
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),  
DesignWare components, Verilog HDL, VHDL, and other interfaces  
to popular EDA tools from manufacturers such as Cadence,  
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,  
VeriBest, and Viewlogic  
Table 3. FLEX 10KE Package Options & I/O Pin Count  
Notes (1), (2)  
Device  
144-Pin 208-Pin 240-Pin 256-Pin 356-Pin 484-Pin 599-Pin 600-Pin 672-Pin  
TQFP  
PQFP  
PQFP  
RQFP  
FineLine  
BGA  
BGA FineLine  
BGA  
PGA  
BGA FineLine  
BGA  
EPF10K30E  
EPF10K50E  
EPF10K50S  
EPF10K100E  
EPF10K130E  
EPF10K200E  
EPF10K200S  
102  
102  
102  
147  
147  
147  
147  
176  
191  
191  
191  
220  
254  
220 (3)  
254 (3)  
254 (3)  
338 (3)  
189  
189  
189  
186  
220  
274  
274  
254  
338  
369  
424  
470  
470  
413  
470  
470  
470  
470  
182  
274  
369  
Notes:  
(1) FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat  
pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA) packages.  
(2) Devices in the same package are pin-compatible, although some devices have more I/ O pins than others. When  
planning device migration, use the I/ O pins that are common to all devices.  
(3) This option is supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all  
FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and  
672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration  
is set.  
Altera Corporation  
3

EPF10K200SRC240-1N 替代型号

型号 品牌 替代类型 描述 数据表
EPF10K200SRC240-1 ALTERA

类似代替

Loadable PLD, 0.3ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-3 ALTERA

类似代替

Loadable PLD, 0.8ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
EPF10K200SRC240-2 ALTERA

类似代替

Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240

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Loadable PLD, 0.6ns, CMOS, PQFP240, 34.60 X 34.60 MM, 0.50 MM PITCH, RQFP-240
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EPF10K200SRC240-2X ALTERA

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EPF10K200SRC240-3N ALTERA

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Loadable PLD, 23.8ns, CMOS, PBGA356, HEAT SINK, BGA-356
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