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EPF10K130EFC484-1 PDF预览

EPF10K130EFC484-1

更新时间: 2024-01-22 02:22:49
品牌 Logo 应用领域
其他 - ETC 现场可编程门阵列可编程逻辑LTE
页数 文件大小 规格书
120页 1759K
描述
Field Programmable Gate Array (FPGA)

EPF10K130EFC484-1 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:BGA, BGA484,22X22,40Reach Compliance Code:compliant
ECCN代码:3A991HTS代码:8542.39.00.01
风险等级:5.15JESD-30 代码:S-PBGA-B484
JESD-609代码:e1长度:23 mm
湿度敏感等级:3I/O 线路数量:369
输入次数:369逻辑单元数量:6656
输出次数:369端子数量:484
最高工作温度:70 °C最低工作温度:
组织:369 I/O输出函数:MIXED
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA484,22X22,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):260
电源:2.5,2.5/3.3 V可编程逻辑类型:LOADABLE PLD
传播延迟:0.3 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:Field Programmable Gate Arrays
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:23 mm
Base Number Matches:1

EPF10K130EFC484-1 数据手册

 浏览型号EPF10K130EFC484-1的Datasheet PDF文件第2页浏览型号EPF10K130EFC484-1的Datasheet PDF文件第3页浏览型号EPF10K130EFC484-1的Datasheet PDF文件第4页浏览型号EPF10K130EFC484-1的Datasheet PDF文件第5页浏览型号EPF10K130EFC484-1的Datasheet PDF文件第6页浏览型号EPF10K130EFC484-1的Datasheet PDF文件第7页 
FLEX 10KE  
Embedded Programmable  
Logic Family  
®
September 2000, ver. 2.10  
Data Sheet  
 
Embedded programmable logic devices (PLDs), providing  
system-on-a-programmable-chip integration in a single device  
Features...  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Logic array for general logic functions  
 
 
High density  
30,000 to 200,000 typical gates (see Tables 1 and 2)  
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be  
used without reducing logic capacity  
System-level features  
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/O performance (t and t ) up to 212 MHz  
Fully compliant with the PCI Special Interest Group (PCI SIG)  
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at  
33 MHz or 66 MHz  
SU  
CO  
-1 speed grade devices are compliant with PCI Local Bus  
Specification, Revision 2.2, for 5.0-V operation  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the  
FLEX 10K Embedded Programmable Logic Family Data Sheet.  
f
Table 1. FLEX 10KE Device Features  
Feature  
EPF10K30E  
EPF10K50E  
EPF10K50S  
EPF10K100B  
Typical gates (1)  
Maximum system gates  
Logic elements (LEs)  
EABs  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
158,000  
4,992  
12  
Total RAM bits  
24,576  
220  
40,960  
254  
24,576  
191  
Maximum user I/O pins  
Altera Corporation  
1
A-DS-F10KE-02.10  

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EPF10K130EFC484-3 ALTERA Loadable PLD, 0.6ns, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484

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EPF10K130EFC484-3N ALTERA Loadable PLD, 0.6ns, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484

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