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EPF10K100EBC672-1 PDF预览

EPF10K100EBC672-1

更新时间: 2023-01-02 20:59:55
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
120页 1957K
描述
Loadable PLD, 0.6ns, PBGA672

EPF10K100EBC672-1 数据手册

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FLEX 10KE  
Embedded Programmable  
Logic Family  
®
June 1999, ver. 2.01  
Data Sheet  
Embedded programmable logic devices (PLDs), providing  
Features...  
System-on-a-Programmable-ChipTM integration in a single device  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Preliminary  
Information  
Logic array for general logic functions  
High density  
30,000 to 200,000 typical gates (see Tables 1 and 2)  
Up to 98,304 RAM bits; 4,096 bits per EAB, all of which can be  
used without reducing logic capacity  
System-level features  
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/O performance (t and t ) up to 250 MHz  
SU  
CO  
Fully compliant with the peripheral component interconnect  
Special Interest Group (PCI SIG) PCI Local Bus Specification,  
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz  
-1 speed grade devices are compliant with PCI Local Bus  
Specification, Revision 2.2, for 5.0-V operation  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
For information on 5.0-V FLEX 10K or 3.3-V FLEX 10KA devices, see the  
FLEX 10K Embedded Programmable Logic Family Data Sheet.  
f
Table 1. FLEX 10KE Device Features  
Feature  
EPF10K30E  
EPF10K50E  
EPF10K50S  
EPF10K100B  
Typical gates (1)  
Maximum system gates  
Logic elements (LEs)  
EABs  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
158,000  
4,992  
12  
Total RAM bits  
24,576  
220  
40,960  
254  
24,576  
191  
Maximum user I/O pins  
Altera Corporation  
1
A-DS-F10KE-02.01  

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