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EPF10K100BPC208-1 PDF预览

EPF10K100BPC208-1

更新时间: 2024-01-10 15:40:26
品牌 Logo 应用领域
阿尔特拉 - ALTERA LTE输入元件可编程逻辑
页数 文件大小 规格书
120页 1901K
描述
Loadable PLD, 11ns, CMOS, PQFP208, 30.60 X 30.60 MM, 0.50 MM PITCH, PLASTIC, QFP-208

EPF10K100BPC208-1 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58Is Samacsys:N
JESD-30 代码:S-PQFP-G208JESD-609代码:e3
长度:28 mm专用输入次数:4
I/O 线路数量:147端子数量:208
最高工作温度:70 °C最低工作温度:
组织:4 DEDICATED INPUTS, 147 I/O输出函数:MIXED
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
可编程逻辑类型:LOADABLE PLD传播延迟:11 ns
认证状态:Not Qualified座面最大高度:4.1 mm
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmBase Number Matches:1

EPF10K100BPC208-1 数据手册

 浏览型号EPF10K100BPC208-1的Datasheet PDF文件第2页浏览型号EPF10K100BPC208-1的Datasheet PDF文件第3页浏览型号EPF10K100BPC208-1的Datasheet PDF文件第4页浏览型号EPF10K100BPC208-1的Datasheet PDF文件第5页浏览型号EPF10K100BPC208-1的Datasheet PDF文件第6页浏览型号EPF10K100BPC208-1的Datasheet PDF文件第7页 
FLEX 10KE  
Embedded Programmable  
Logic Family  
®
September 2000, ver. 2.10  
Data Sheet  
 
Embedded programmable logic devices (PLDs), providing  
system-on-a-programmable-chip integration in a single device  
Features...  
Enhanced embedded array for implementing megafunctions  
such as efficient memory and specialized logic functions  
Dual-port capability with up to 16-bit width per embedded array  
block (EAB)  
Logic array for general logic functions  
 
 
High density  
30,000 to 200,000 typical gates (see Tables 1 and 2)  
Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be  
used without reducing logic capacity  
System-level features  
MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or  
5.0-V devices  
Low power consumption  
Bidirectional I/O performance (t and t ) up to 212 MHz  
Fully compliant with the PCI Special Interest Group (PCI SIG)  
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at  
33 MHz or 66 MHz  
SU  
CO  
-1 speed grade devices are compliant with PCI Local Bus  
Specification, Revision 2.2, for 5.0-V operation  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the  
FLEX 10K Embedded Programmable Logic Family Data Sheet.  
f
Table 1. FLEX 10KE Device Features  
Feature  
EPF10K30E  
EPF10K50E  
EPF10K50S  
EPF10K100B  
Typical gates (1)  
Maximum system gates  
Logic elements (LEs)  
EABs  
30,000  
119,000  
1,728  
6
50,000  
199,000  
2,880  
10  
100,000  
158,000  
4,992  
12  
Total RAM bits  
24,576  
220  
40,960  
254  
24,576  
191  
Maximum user I/O pins  
Altera Corporation  
1
A-DS-F10KE-02.10  

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