Datasheet > EPF10K100B

EPF10K100B

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
1页	60K
描述
Embedded Programmable Logic Device

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EPF10K100B 数据手册

EPF10K100B

Embedded Programmable

Logic Device

July 1998, ver. 1

Errata Sheet

This errata sheet provides updated information for Revision A and

Revision B EPF10K100B devices. The die revision is indicated by the third

digit of the nine-digit code on the top side of the device. Revision C and

higher EPF10K100B devices do not exhibit the conditions described in this

document.

Preliminary

Information

Under certain voltage conditions, the output buffer delay for Revision A

and Revision B EPF10K100B devices is slower than the reported value for

I/O pins with the Slow Slew Rate option turned on in the MAX+PLUS II

software. The MAX+PLUS II version 9.0 Timing Analyzer and Simulator

report an added output delay of 4.5 ns when the Slow Slew Rate option is

turned on. When the Slow Slew Rate option is turned on and the VCCINT

and VCCIOpins are powered at 2.3 V and 3.6 V, respectively, the change

in the measured output buffer delay due to the Slow Slew Rate option

may be as high as 7.5 ns.

This condition in which the VCCINTand VCCIOpins are powered to the

opposite extremes is rare. For designs where this increased delay is a

problem, you should either turn off the Slow Slew Rate option or adjust

the circuit’s power supply to provide a 2.5-V V

CCINT

With the Slow Slew Rate option turned off, the device functions as

reported in the MAX+PLUS II version 9.0 Timing Analyzer and

Simulator.

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Marketing:

(408) 544-7104

Literature Services:

(888) 3-ALTERA

Altera, EPF10K100B, MAX, MAX+PLUS, and MAX+PLUS II are trademarks and/or service marks of Altera

Corporation in the United States and other countries. Altera acknowledges the trademarks of other

organizations for their respective products or services mentioned in this document. Altera products are

protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and

copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance

with Altera’s standard warranty, but reserves the right to make changes to any products and services at any

time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by

Altera Corporation. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for

products or services.

lit_req@altera.com

Altera Corporation

A-ES-10K100B-1.0

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与EPF10K100B相关器件

型号	品牌	描述	获取价格	数据表
EPF10K100BC560-4	ALTERA	Loadable PLD, 23.8ns, CMOS, PBGA560, BGA-560	获取价格
EPF10K100BFC256-1	ALTERA	Loadable PLD, 11ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256	获取价格
EPF10K100BFC256-1DX	ETC	ASIC	获取价格
EPF10K100BFC256-2	ALTERA	Loadable PLD, 12ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256	获取价格
EPF10K100BFC256-2DX	ETC	ASIC	获取价格
EPF10K100BFC256-3	ALTERA	Loadable PLD, 14.5ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FINE LINE, BGA-256	获取价格

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