Datasheet > EPF10K100ABC356-2

EPF10K100ABC356-2

更新时间： 2024-02-19 04:32:49

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
143页	1990K
描述
Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356

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EPF10K100ABC356-2 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	LBGA, BGA356,26X26,50	Reach Compliance Code：	compliant
ECCN代码：	3A991	HTS代码：	8542.39.00.01
风险等级：	5.05	JESD-30 代码：	S-PBGA-B356
JESD-609代码：	e1	长度：	35 mm
湿度敏感等级：	3	专用输入次数：	4
I/O 线路数量：	274	输入次数：	274
逻辑单元数量：	4992	输出次数：	274
端子数量：	356	最高工作温度：	70 °C
最低工作温度：		组织：	4 DEDICATED INPUTS, 274 I/O
输出函数：	REGISTERED	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA356,26X26,50
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	245	电源：	2.5/3.3,3.3 V
可编程逻辑类型：	LOADABLE PLD	传播延迟：	0.7 ns
认证状态：	Not Qualified	座面最大高度：	1.63 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	35 mm	Base Number Matches：	1

EPF10K100ABC356-2 数据手册

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FLEX 10K Embedded Programmable Logic Device Family Data Sheet

For more information, see the following documents:

ꢀ

Configuration Devices for APEX & FLEX Devices Data Sheet

BitBlaster Serial Download Cable Data Sheet

ByteBlasterMV Parallel Port Download Cable Data Sheet

Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000

Devices)

FLEX 10K devices are supported by Altera development systems; single,

integrated packages that offer schematic, text (including AHDL), and

waveform design entry, compilation and logic synthesis, full simulation

and worst-case timing analysis, and device configuration. The Altera

software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and

other interfaces for additional design entry and simulation support from

other industry-standard PC- and UNIX workstation-based EDA tools.

The Altera software works easily with common gate array EDA tools for

synthesis and simulation. For example, the Altera software can generate

Verilog HDL files for simulation with tools such as Cadence Verilog-XL.

Additionally, the Altera software contains EDA libraries that use device-

specific features such as carry chains which are used for fast counter and

arithmetic functions. For instance, the Synopsys Design Compiler library

supplied with the Altera development systems include DesignWare

functions that are optimized for the FLEX 10K architecture.

The Altera development systems run on Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/ 800 workstations.

See the MAX+PLUS II Programmable Logic Development System & Software

Data Sheet for more information.

Functional

Each FLEX 10K device contains an embedded array to implement

memory and specialized logic functions, and a logic array to implement

general logic.

Description

The embedded array consists of a series of EABs. When implementing

memory functions, each EAB provides 2,048 bits, which can be used to

create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.

When implementing logic, each EAB can contribute 100 to 600 gates

towards complex logic functions, such as multipliers, microcontrollers,

state machines, and DSP functions. EABs can be used independently, or

multiple EABs can be combined to implement larger functions.

Altera Corporation

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与EPF10K100ABC356-2相关器件

型号	品牌	描述	获取价格	数据表
EPF10K100ABC356-2N	INTEL	Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356	获取价格
EPF10K100ABC356-2N	ALTERA	Loadable PLD, 0.7ns, CMOS, PBGA356, BGA-356	获取价格
EPF10K100ABC356-3	ALTERA	Embedded Programmable Logic Device Family	获取价格
EPF10K100ABC356-3	INTEL	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356	获取价格
EPF10K100ABC356-3N	ALTERA	Loadable PLD, 0.8ns, CMOS, PBGA356, BGA-356	获取价格
EPF10K100ABC600-1	ALTERA	Loadable PLD, 0.6ns, CMOS, PBGA600, BGA-600	获取价格

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