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EP4CE55F23C8N PDF预览

EP4CE55F23C8N

更新时间: 2024-02-14 09:42:53
品牌 Logo 应用领域
英特尔 - INTEL 时钟可编程逻辑
页数 文件大小 规格书
44页 663K
描述
Field Programmable Gate Array, 3491 CLBs, 472.5MHz, 55856-Cell, PBGA484, 23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484

EP4CE55F23C8N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:1.61
最大时钟频率:472.5 MHzJESD-30 代码:S-PBGA-B484
JESD-609代码:e1长度:23 mm
湿度敏感等级:3可配置逻辑块数量:3491
输入次数:327逻辑单元数量:55856
输出次数:327端子数量:484
最高工作温度:85 °C最低工作温度:
组织:3491 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA484,22X22,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.4 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.25 V最小供电电压:1.15 V
标称供电电压:1.2 V表面贴装:YES
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:23 mmBase Number Matches:1

EP4CE55F23C8N 数据手册

 浏览型号EP4CE55F23C8N的Datasheet PDF文件第2页浏览型号EP4CE55F23C8N的Datasheet PDF文件第3页浏览型号EP4CE55F23C8N的Datasheet PDF文件第4页浏览型号EP4CE55F23C8N的Datasheet PDF文件第6页浏览型号EP4CE55F23C8N的Datasheet PDF文件第7页浏览型号EP4CE55F23C8N的Datasheet PDF文件第8页 
Chapter 1: Cyclone IV Device Datasheet  
1–5  
Operating Conditions  
Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices (1), (2) (Part 2 of 2)  
Symbol  
IDiode  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
mA  
Magnitude of DC current across  
PCI-clamp diode when enable  
10  
Notes to Table 1–3:  
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support  
C6, C7, C8, I7, and A7 speed grades.  
(2) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used)  
and must be powered up and powered down at the same time.  
(3) VCC must rise monotonically.  
(4) VCCIO powers all input buffers.  
(5) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range  
within 50 ms.  
(6) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within  
3 ms.  
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 1 of 2)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Core voltage, PCIe hard IP block, and  
transceiver PCS power supply  
(3)  
VCCINT  
1.16  
1.2  
1.24  
V
(1), (3)  
VCCA  
VCCD_PLL  
PLL analog power supply  
PLL digital power supply  
2.375  
1.16  
2.5  
1.2  
2.625  
1.24  
V
V
(2)  
I/O banks power supply for 3.3-V  
operation  
3.135  
2.85  
3.3  
3
3.465  
3.15  
V
V
V
V
V
V
V
V
V
V
V
I/O banks power supply for 3.0-V  
operation  
I/O banks power supply for 2.5-V  
operation  
2.375  
1.71  
2.5  
1.8  
1.5  
1.2  
3.3  
3
2.625  
1.89  
(3), (4)  
VCCIO  
I/O banks power supply for 1.8-V  
operation  
I/O banks power supply for 1.5-V  
operation  
1.425  
1.14  
1.575  
1.26  
I/O banks power supply for 1.2-V  
operation  
Differential clock input pins power  
supply for 3.3-V operation  
3.135  
2.85  
3.465  
3.15  
Differential clock input pins power  
supply for 3.0-V operation  
Differential clock input pins power  
supply for 2.5-V operation  
2.375  
1.71  
2.5  
1.8  
1.5  
2.625  
1.89  
VCC_CLKIN  
(3), (5), (6)  
Differential clock input pins power  
supply for 1.8-V operation  
Differential clock input pins power  
supply for 1.5-V operation  
1.425  
1.575  
Differential clock input pins power  
supply for 1.2-V operation  
1.14  
1.2  
2.5  
1.26  
V
V
VCCH_GXB  
Transceiver output buffer power supply  
2.375  
2.625  
March 2016 Altera Corporation  
Cyclone IV Device Handbook,  
Volume 3  

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