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EP4CE55F23C8N PDF预览

EP4CE55F23C8N

更新时间： 2024-02-05 22:39:36
品牌 Logo 应用领域
英特尔 - INTEL 时钟栅可编程逻辑
页数 文件大小 规格书
44页 663K
描述
Field Programmable Gate Array, 3491 CLBs, 472.5MHz, 55856-Cell, PBGA484, 23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484

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EP4CE55F23C8N 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-484Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.61
最大时钟频率：472.5 MHzJESD-30 代码：S-PBGA-B484
JESD-609代码：e1长度：23 mm
湿度敏感等级：3可配置逻辑块数量：3491
输入次数：327逻辑单元数量：55856
输出次数：327端子数量：484
最高工作温度：85 °C最低工作温度：
组织：3491 CLBS封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA484,22X22,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：260电源：1.2,1.2/3.3,2.5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.4 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.25 V最小供电电压：1.15 V
标称供电电压：1.2 V表面贴装：YES
温度等级：OTHER端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：23 mmBase Number Matches：1

EP4CE55F23C8N 数据手册

 浏览型号EP4CE55F23C8N的Datasheet PDF文件第1页浏览型号EP4CE55F23C8N的Datasheet PDF文件第3页浏览型号EP4CE55F23C8N的Datasheet PDF文件第4页浏览型号EP4CE55F23C8N的Datasheet PDF文件第5页浏览型号EP4CE55F23C8N的Datasheet PDF文件第6页浏览型号EP4CE55F23C8N的Datasheet PDF文件第7页 
1–2  
Chapter 1: Cyclone IV Device Datasheet  
Operating Conditions  
1
Cyclone IV E industrial devices I7 are offered with extended operating temperature  
range.  
Absolute Maximum Ratings  
Absolute maximum ratings define the maximum operating conditions for Cyclone IV  
devices. The values are based on experiments conducted with the device and  
theoretical modeling of breakdown and damage mechanisms. The functional  
operation of the device is not implied at these conditions. Table 1–1 lists the absolute  
maximum ratings for Cyclone IV devices.  
c
Conditions beyond those listed in Table 1–1 cause permanent damage to the device.  
Additionally, device operation at the absolute maximum ratings for extended periods  
of time have adverse effects on the device.  
Table 1–1. Absolute Maximum Ratings for Cyclone IV Devices (1)  
Symbol  
VCCINT  
VCCA  
Parameter  
Min  
Max  
Unit  
Core voltage, PCI Express(PCIe) hard IP  
block, and transceiver physical coding sublayer  
(PCS) power supply  
–0.5  
1.8  
V
Phase-locked loop (PLL) analog power supply  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
3.75  
1.8  
V
V
V
V
V
VCCD_PLL PLL digital power supply  
VCCIO I/O banks power supply  
3.75  
4.5  
VCC_CLKIN Differential clock input pins power supply  
VCCH_GXB Transceiver output buffer power supply  
3.75  
Transceiver physical medium attachment (PMA)  
and auxiliary power supply  
VCCA_GXB  
–0.5  
3.75  
V
VCCL_GXB Transceiver PMA and auxiliary power supply  
–0.5  
–0.5  
–25  
–65  
–40  
1.8  
4.2  
40  
V
V
VI  
DC input voltage  
IOUT  
TSTG  
TJ  
DC output current, per pin  
Storage temperature  
mA  
°C  
°C  
150  
125  
Operating junction temperature  
Note to Table 1–1:  
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the  
power supply.  
Maximum Allowed Overshoot or Undershoot Voltage  
During transitions, input signals may overshoot to the voltage shown in Table 1–2 and  
undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods  
shorter than 20 ns. Table 1–2 lists the maximum allowed input overshoot voltage and  
the duration of the overshoot voltage as a percentage over the lifetime of the device.  
The maximum allowed overshoot duration is specified as a percentage of high-time  
over the lifetime of the device.  
Cyclone IV Device Handbook,  
Volume 3  
March 2016 Altera Corporation  
1234567...44

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