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EP3CLS200F780C7 PDF预览

EP3CLS200F780C7

更新时间: 2024-02-23 12:36:38
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟可编程逻辑
页数 文件大小 规格书
14页 306K
描述
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780

EP3CLS200F780C7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:LEAD FREE, FBGA-780针数:780
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.39.00.01风险等级:5.24
最大时钟频率:450 MHzJESD-30 代码:S-PBGA-B780
JESD-609代码:e1长度:29 mm
湿度敏感等级:3可配置逻辑块数量:198464
输入次数:413逻辑单元数量:198464
输出次数:413端子数量:780
最高工作温度:85 °C最低工作温度:
组织:198464 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA780,28X28,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1.2,1.2/3.3,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.4 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.25 V最小供电电压:1.15 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:29 mm
Base Number Matches:1

EP3CLS200F780C7 数据手册

 浏览型号EP3CLS200F780C7的Datasheet PDF文件第1页浏览型号EP3CLS200F780C7的Datasheet PDF文件第2页浏览型号EP3CLS200F780C7的Datasheet PDF文件第4页浏览型号EP3CLS200F780C7的Datasheet PDF文件第5页浏览型号EP3CLS200F780C7的Datasheet PDF文件第6页浏览型号EP3CLS200F780C7的Datasheet PDF文件第7页 
Chapter 1: Cyclone III Device Family Overview  
1–3  
Cyclone III Device Family Features  
Wide collection of pre-built and verified IP cores from Altera and Altera  
Megafunction Partners Program (AMPP) partners  
Supports high-speed external memory interfaces such as DDR, DDR2,  
SDR SDRAM, and QDRII SRAM  
Auto-calibrating PHY feature eases the timing closure process and eliminates  
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces  
Cyclone III device family supports vertical migration that allows you to migrate your  
device to other devices with the same dedicated pins, configuration pins, and power  
pins for a given package-across device densities. This allows you to optimize device  
density and cost as your design evolves.  
Table 1–1 lists Cyclone III device family features.  
Table 1–1. Cyclone III Device Family Features  
Number of  
Global  
Clock  
Networks  
Logic  
Elements  
Total RAM  
Bits  
18 x 18  
Multipliers  
Maximum  
User I/Os  
Family  
Device  
M9K  
PLLs  
Blocks  
EP3C5  
EP3C10  
5,136  
10,320  
15,408  
24,624  
39,600  
55,856  
81,264  
119,088  
70,208  
100,448  
150,848  
198,464  
46  
46  
423,936  
423,936  
23  
23  
2
2
4
4
4
4
4
4
4
4
4
4
10  
10  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
182  
182  
346  
215  
535  
377  
429  
531  
429  
429  
429  
429  
EP3C16  
56  
516,096  
56  
EP3C25  
66  
608,256  
66  
Cyclone III  
EP3C40  
126  
260  
305  
432  
333  
483  
666  
891  
1,161,216  
2,396,160  
2,810,880  
3,981,312  
3,068,928  
4,451,328  
6,137,856  
8,211,456  
126  
156  
244  
288  
200  
276  
320  
396  
EP3C55  
EP3C80  
EP3C120  
EP3CLS70  
EP3CLS100  
EP3CLS150  
EP3CLS200  
Cyclone III  
LS  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
 

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