Datasheet > EP3CLS200F780C7

EP3CLS200F780C7

更新时间： 2024-01-22 17:02:01

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟栅可编程逻辑
页数	文件大小	规格书
14页	306K
描述
Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780

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EP3CLS200F780C7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LEAD FREE, FBGA-780	针数：	780
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.39.00.01	风险等级：	5.24
最大时钟频率：	450 MHz	JESD-30 代码：	S-PBGA-B780
JESD-609代码：	e1	长度：	29 mm
湿度敏感等级：	3	可配置逻辑块数量：	198464
输入次数：	413	逻辑单元数量：	198464
输出次数：	413	端子数量：	780
最高工作温度：	85 °C	最低工作温度：
组织：	198464 CLBS	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA780,28X28,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	245	电源：	1.2,1.2/3.3,2.5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.25 V	最小供电电压：	1.15 V
标称供电电压：	1.2 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	29 mm
Base Number Matches：	1

EP3CLS200F780C7 数据手册

Chapter 1: Cyclone III Device Family Overview

1–7

Cyclone III Device Family Architecture

Memory Blocks

Each M9K memory block of the Cyclone III device family provides nine Kbits of

on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up

to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of

M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO)

buffers, or ROM. The Cyclone III device family memory blocks are optimized for

applications such as high throughout packet processing, embedded processor

program, and embedded data storage.

The Quartus II software allows you to take advantage of the M9K memory blocks by

instantiating memory using a dedicated megafunction wizard or by inferring memory

directly from the VHDL or Verilog source code.

M9K memory blocks support single-port, simple dual-port, and true dual-port

operation modes. Single-port mode and simple dual-port mode are supported for all

port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True

dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16,

and ×18.

For more information about memory blocks, refer to the Memory Blocks in the Cyclone

III Device Family chapter.

Embedded Multipliers and Digital Signal Processing Support

Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS

devices support up to 396 embedded multiplier blocks. Each block supports one

individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.

The Quartus II software includes megafunctions that are used to control the operation

mode of the embedded multiplier blocks based on user parameter settings.

Multipliers can also be inferred directly from the VHDL or Verilog source code. In

addition to embedded multipliers, Cyclone III device family includes a combination

of on-chip resources and external interfaces, making them ideal for increasing

performance, reducing system cost, and lowering the power consumption of digital

signal processing (DSP) systems. You can use Cyclone III device family alone or as

DSP device co-processors to improve price-to-performance ratios of DSP systems.

The Cyclone III device family DSP system design support includes the following

features:

■

DSP IP cores:

■

Common DSP processing functions such as finite impulse response (FIR), fast

Fourier transform (FFT), and numerically controlled oscillator (NCO) functions

Suites of common video and image processing functions

■

Complete reference designs for end-market applications

DSP Builder interface tool between the Quartus II software and the MathWorks

Simulink and MATLAB design environments

■

DSP development kits

For more information about embedded multipliers and digital signal processing

support, refer to the Embedded Multipliers in Cyclone III Devices chapter.

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 1

1...4 5 678 9 10...14

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与EP3CLS200F780C7相关器件

型号	品牌	描述	获取价格	数据表
EP3CLS200F780C7N	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS200F780C7N	ALTERA	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS200F780C8	ALTERA	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM	获取价格
EP3CLS200F780C8	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM	获取价格
EP3CLS200F780C8N	INTEL	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, LEAD FREE,	获取价格
EP3CLS200F780I7	ALTERA	Field Programmable Gate Array, 198464 CLBs, 450MHz, 198464-Cell, CMOS, PBGA780, 29 X 29 MM	获取价格

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