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EP20K200FC484-2XN PDF预览

EP20K200FC484-2XN

更新时间: 2024-01-20 20:32:50
品牌 Logo 应用领域
阿尔特拉 - ALTERA LTE可编程逻辑
页数 文件大小 规格书
117页 593K
描述
Field Programmable Gate Array, 8320-Cell, CMOS, PBGA484

EP20K200FC484-2XN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:BGA, BGA484,22X22,40Reach Compliance Code:compliant
风险等级:5.8JESD-30 代码:S-PBGA-B484
JESD-609代码:e1湿度敏感等级:3
输入次数:376逻辑单元数量:8320
输出次数:376端子数量:484
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA484,22X22,40封装形状:SQUARE
封装形式:GRID ARRAY电源:2.5,2.5/3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
子类别:Field Programmable Gate Arrays表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

EP20K200FC484-2XN 数据手册

 浏览型号EP20K200FC484-2XN的Datasheet PDF文件第2页浏览型号EP20K200FC484-2XN的Datasheet PDF文件第3页浏览型号EP20K200FC484-2XN的Datasheet PDF文件第4页浏览型号EP20K200FC484-2XN的Datasheet PDF文件第5页浏览型号EP20K200FC484-2XN的Datasheet PDF文件第6页浏览型号EP20K200FC484-2XN的Datasheet PDF文件第7页 
APEX 20K  
Programmable Logic  
Device Family  
March 2004, ver. 5.1  
Data Sheet  
Industry’s first programmable logic device (PLD) incorporating  
system-on-a-programmable-chip (SOPC) integration  
Features  
MultiCoreTM architecture integrating look-up table (LUT) logic,  
product-term logic, and embedded memory  
LUT logic used for register-intensive functions  
Embedded system block (ESB) used to implement memory  
functions, including first-in first-out (FIFO) buffers, dual-port  
RAM, and content-addressable memory (CAM)  
ESB implementation of product-term logic used for  
combinatorial-intensive functions  
High density  
30,000 to 1.5 million typical gates (see Tables 1 and 2)  
Up to 51,840 logic elements (LEs)  
Up to 442,368 RAM bits that can be used without reducing  
available logic  
Up to 3,456 product-term-based macrocells  
Table 1. APEX 20K Device Features Note (1)  
Feature  
EP20K30E EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E  
Maximum  
system  
gates  
113,000  
162,000  
263,000  
263,000  
404,000  
526,000  
526,000  
Typical  
gates  
30,000  
60,000  
100,000  
100,000  
160,000  
200,000  
200,000  
LEs  
1,200  
12  
2,560  
16  
4,160  
26  
4,160  
26  
6,400  
40  
8,320  
52  
8,320  
52  
ESBs  
Maximum  
RAM bits  
24,576  
32,768  
53,248  
53,248  
81,920  
106,496  
106,496  
Maximum  
macrocells  
192  
128  
256  
196  
416  
252  
416  
246  
640  
316  
832  
382  
832  
376  
Maximum  
user I/O  
pins  
Altera Corporation  
1
DS-APEX20K-5.1  
 

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