Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
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Advanced interconnect structure
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Four-level hierarchical FastTrack® Interconnect structure
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
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Advanced packaging options
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Available in a variety of packages with 144 to 1,020 pins (see
Tables 3 through 6)
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FineLine BGATM packages maximize board space efficiency
SameFrameTM pin migration providing migration capability
across device densities and package sizes
Advanced software support
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Software design support and automatic place-and-route
provided by the Altera® QuartusTM development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
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Altera MegaCoreTM functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
Quartus SignalTapTM embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
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Supports popular revision-control software packages including
PVCS, RCS, and SCCS
Altera Corporation
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