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EP20K100BI324-3 PDF预览

EP20K100BI324-3

更新时间: 2023-03-15 00:00:00
品牌 Logo 应用领域
阿尔特拉 - ALTERA /
页数 文件大小 规格书
68页 930K
描述
Loadable PLD, PBGA324

EP20K100BI324-3 数据手册

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Preliminary Information  
APEX 20K Programmable Logic Device Family Data Sheet  
Advanced interconnect structure  
Four-level hierarchical FastTrack® Interconnect structure  
providing fast, predictable interconnect delays  
Dedicated carry chain that implements arithmetic functions such  
as fast adders, counters, and comparators (automatically used by  
software tools and megafunctions)  
Dedicated cascade chain that implements high-speed,  
high-fan-in logic functions (automatically used by software tools  
and megafunctions)  
Interleaved local interconnect allows one LE to drive 29 other  
LEs through the fast local interconnect  
Advanced packaging options  
Available in a variety of packages with 144 to 1,020 pins (see  
Tables 3 through 6)  
FineLine BGATM packages maximize board space efficiency  
SameFrameTM pin migration providing migration capability  
across device densities and package sizes  
Advanced software support  
Software design support and automatic place-and-route  
provided by the Altera® QuartusTM development system for  
Windows-based PCs, Sun SPARCstations, and HP 9000  
Series 700/800 workstations  
Altera MegaCoreTM functions and Altera Megafunction Partners  
Program (AMPPSM) megafunctions  
NativeLinkTM integration with popular synthesis, simulation,  
and timing analysis tools  
Quartus SignalTapTM embedded logic analyzer simplifies  
in-system design evaluation by giving access to internal nodes  
during device operation  
Supports popular revision-control software packages including  
PVCS, RCS, and SCCS  
Altera Corporation  
3

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