Datasheet > EP20K100BI324-3

EP20K100BI324-3

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
68页	930K
描述
Loadable PLD, PBGA324

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EP20K100BI324-3 数据手册

Preliminary Information

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20K devices are configured at system power-up with data stored in

an Altera serial configuration device or provided by a system controller.

Altera offers the in-system programmability (ISP)-capable EPC2

configuration devices, which configure APEX 20K devices via a serial

data stream. Moreover, APEX 20K devices contain an optimized interface

that permits microprocessors to configure APEX 20K devices serially or in

parallel, and synchronously or asynchronously. The interface also enables

microprocessors to treat APEX 20K devices as memory and configure the

device by writing to a virtual memory location, making reconfiguration

easy.

Contact Altera for information on future configuration devices.

After an APEX 20K device has been configured, it can be reconfigured

in-circuit by resetting the device and loading new data. Real-time changes

can be made during system operation, enabling innovative reconfigurable

computing applications.

APEX 20K devices are supported by Altera’s Quartus development

system, a single, integrated package that offers HDL and schematic design

entry, compilation and logic synthesis, full simulation and worst-case

timing analysis, SignalTap logic analysis, and device configuration. The

Quartus software runs on Windows-based PCs, Sun SPARCstations, and

HP 9000 Series 700/800 workstations.

The Quartus software provides NativeLink interfaces to other industry-

standard PC- and UNIX workstation-based EDA tools. For example,

designers can invoke the Quartus software from within third-party design

tools. Further, the Quartus software contains built-in optimized synthesis

libraries; synthesis tools can use these libraries to optimize designs for

APEX 20K devices. For example, the Synopsys Design Compiler library,

supplied with the Quartus development system, includes DesignWare

functions optimized for the APEX 20K architecture.

APEX 20K devices incorporate LUT-based logic, product-term-based

logic, and memory into one device. Signal interconnections within

APEX 20K devices (as well as to and from device pins) are provided by the

FastTrack Interconnect—a series of fast, continuous row and column

channels that run the entire length and width of the device.

Functional

Description

Altera Corporation

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