Datasheet > EP1S120F1923C6

EP1S120F1923C6

更新时间： 2024-01-16 17:07:31

品牌	Logo	应用领域
阿尔特拉 - ALTERA		栅可编程逻辑
页数	文件大小	规格书
196页	1020K
描述
Field Programmable Gate Array, 13130 CLBs, CMOS, PBGA1923, 45 X 45 MM, 1 MM PITCH, FBGA-1923

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EP1S120F1923C6 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	1923	Reach Compliance Code：	compliant
风险等级：	5.86	JESD-30 代码：	S-PBGA-B1923
JESD-609代码：	e1	可配置逻辑块数量：	13130
端子数量：	1923	最高工作温度：	85 °C
最低工作温度：		组织：	13130 CLBS
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子位置：	BOTTOM	Base Number Matches：	1

EP1S120F1923C6 数据手册

Stratix

Programmable Logic

Device Family

April 2002, ver. 2.0

Data Sheet

The Stratix family of programmable logic devices (PLDs) is based on a

1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to

114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices

offer up to 28 digital signal processing (DSP) blocks with up to

224 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications

that enable efficient implementation of high-performance filters and

multipliers. Stratix devices support various I/ O standards and also offer

a complete clock management solution with its hierarchical clock

structure with up to 420-MHz performance and up to 12 phase-locked

loops (PLLs).

Introduction

Preliminary

Information

■

10,570 to 114,140 LEs; see Table 1

Features...

Up to 10,118,016 RAM bits (1,264,752 bytes) available without

reducing logic resources

TriMatrix^TMmemory consisting of three RAM block sizes to

implement true dual-port memory and first-in first-out (FIFO)

buffers up to 312 MHz

High-speed DSP blocks provide dedicated implementation of

multipliers (at up to 250 MHz), multiply- accumulate functions, and

finite impulse response (FIR) filters

■

Up to 16 global clocks with 22 clocking resources per device region

Up to 12 enhanced PLLs per device provide spread spectrum,

programmable bandwidth, clock switch-over, real-time PLL

reconfiguration, and advanced multiplication and phase shifting

Support for numerous single-ended and differential I/ O standards

High-speed differential I/ O support on up to 116 channels with up to

80 channels optimized for 840 megabits per second (Mbps)

Support for high-speed networking and communications bus

standards including RapidIO, UTOPIA IV, CSIX, HyperTransport^TM

technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and

SFI-4

■

Terminator^TMtechnology provides on-chip termination for

differential and single-ended I/ O pins with impedance matching

Support for high-speed external memory, including zero bus

turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,

double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and

single data rate (SDR) SDRAM

■

Support for multiple intellectual property megafunctions from Altera

MegaCore^®functions and Altera Megafunction Partners Program

(AMPP^SM) megafunctions

Support for remote configuration updates

Altera Corporation

DS-STXFAMLY-2.0

12 3 4 5 6 7...196

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与EP1S120F1923C6相关器件

型号	品牌	获取价格	描述	数据表
EP1S120F1923C7	ALTERA	获取价格	Field Programmable Gate Array, 13130 CLBs, CMOS, PBGA1923, 45 X 45 MM, 1 MM PITCH, FBGA-19
EP1S20	ALTERA	获取价格	This datasheet describes enhanced configuration (EPC) devices
EP1S20B1508C5ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B1508C6ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B1508C7ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B1508I5ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B1508I6ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B1508I7ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1
EP1S20B672C7N	ALTERA	获取价格	Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM P
EP1S20F1508C5ES	ALTERA	获取价格	Stratix Device Handbook, Volume 1

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