Datasheet > EP1C12Q100C6

EP1C12Q100C6

更新时间： 2024-11-14 04:10:27

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
94页	1066K
描述
Cyclone FPGA Family

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EP1C12Q100C6 数据手册

Cyclone

FPGA Family

March 2003, ver. 1.1

Data Sheet

The Cyclone^TMfield programmable gate array family is based on a 1.5-V,

0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost-effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

Introduction

Preliminary

Information

■

2,910 to 20,060 LEs, see Table 1

Up to 294,912 RAM bits (36,864 bytes)

Supports configuration through low-cost serial configuration device

Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

Support for 66-MHz, 32-bit PCI standard

Low speed (311 Mbps) LVDS I/O support

Up to two PLLs per device provide clock multiplication and phase

shifting

Features...

■

Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

Support for multiple intellectual property (IP) cores, including

Altera MegaCore functions and Altera Megafunctions Partners

Program (AMPP^SM) megafunctions

Table 1. Cyclone Device Features

Feature

EP1C3

EP1C4

EP1C6

EP1C12

EP1C20

LEs

2,910

4,000

5,980

12,060

20,060

M4K RAM blocks (128 × 36 bits)

Total RAM bits

59,904

78,336

92,160

239,616

294,912

PLLs

Maximum user I/O pins (1)

104

301

185

249

301

Note to Table 1:

(1) This parameter includes global clock pins.

Altera Corporation

DS-CYCLONE-1.1

12 3 4 5 6 7...94

中文翻译

下载PDF

与EP1C12Q100C6相关器件

型号	品牌	获取价格	描述	数据表
EP1C12Q100C6ES	ALTERA	获取价格	Cyclone FPGA Family Data Sheet
EP1C12Q100C7	ALTERA	获取价格	Cyclone FPGA Family
EP1C12Q100C7ES	ALTERA	获取价格	Cyclone FPGA Family Data Sheet
EP1C12Q100C8	ALTERA	获取价格	Cyclone FPGA Family
EP1C12Q100C8ES	ALTERA	获取价格	Cyclone FPGA Family Data Sheet
EP1C12Q100I6	ALTERA	获取价格	Cyclone FPGA Family
EP1C12Q100I6ES	ALTERA	获取价格	Cyclone FPGA Family Data Sheet
EP1C12Q100I7	ALTERA	获取价格	Cyclone FPGA Family
EP1C12Q100I7ES	ALTERA	获取价格	Cyclone FPGA Family Data Sheet
EP1C12Q100I8	ALTERA	获取价格	Cyclone FPGA Family