Datasheet > EN71NS128B0

EN71NS128B0

更新时间： 2022-12-18 00:37:49

品牌	Logo	应用领域
EON		闪存
页数	文件大小	规格书
8页	637K
描述
Stacked Multi-Chip Product (MCP) Flash Memory and RAM

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数据手册

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EN71NS128B0 数据手册

EN71NS128B0

Pin Description

Signal

Description

A22–A16

Address Inputs

A/DQ15–A/DQ0 Multiplexed Address / Data input / output

CE#

OE#

Chip Enable Input. Asynchronous relative to CLK for the Burst mode.

Output Enable Input. Asynchronous relative to CLK for the Burst mode.

WE#

Write Enable Input.

VCCQ/VCC

VSSQ/GND

Device Power Supply (1.65 V–1.95 V).

Ground

No Connect; not connected internally

RDY

Ready output; indicates the status of the Burst read. V_OL= data invalid, V_OH= data valid.

The first rising edge of CLK in conjunction with AVD# low latches address input and

activates burst mode operation. After the initial word is output, subsequent rising edges

of CLK increment the internal address counter. CLK should remain low during

asynchronous access.

CLK

Address Valid input. Indicates to device that the valid address is present on the address

inputs (address bits A15–A0 are multiplexed, address bits A21–A16 are address only).

V_IL= for asynchronous mode, indicates valid address; for burst mode, causes starting

address to be latched on rising edge of CLK.

AVD#

V_IH= device ignores address inputs

RESET#

WP#

Hardware reset input. V_IL= device resets and returns to reading array data

Hardware write protect input. V_IL= disables writes to SA129-130. Should be at V_IHfor all

other conditions.

At 11 V, accelerates programming; automatically places device in Accelerated Program

mode. At V_IL, disables program and erase functions. Should be at V_IHfor all other

conditions. (Applying high voltage on MCP package is prohibited; otherwise, internal

RAM may be damaged easily!)

ACC

CRE

Control register enable: when CRE is high, WRITE operations laod the RCR or BCR,

and READ operations access the RCR, BCR, or DIDR.

Lower byte enable. DQ7~DQ0

LB#

UB#

Upper byte enable. DQ8~DQ15

Provides data-valid feedback during burst READ and WRITE operations, WAIT is used

to arbitrate collisions between refresh and wrapping within the burst length. WAIT should

be ignored during asynchronous operation. WAIT is High-Z when CE# is HIGH

WAIT

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. A, Issue Date: 2009/7/24

1 2 345 6 7 8

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