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EM6682WS27 PDF预览

EM6682WS27

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
EMMICRO 微控制器
页数 文件大小 规格书
61页 1744K
描述
Ultra Low Power 8-pin Microcontroller

EM6682WS27 数据手册

 浏览型号EM6682WS27的Datasheet PDF文件第4页浏览型号EM6682WS27的Datasheet PDF文件第5页浏览型号EM6682WS27的Datasheet PDF文件第6页浏览型号EM6682WS27的Datasheet PDF文件第8页浏览型号EM6682WS27的Datasheet PDF文件第9页浏览型号EM6682WS27的Datasheet PDF文件第10页 
R
EM6682  
4. Reset  
Figure 6. illustrates the reset structure of the EM6682. One can see that there are five possible reset sources :  
(1) Internal initial Power On Reset (POR) circuitry with Power-Check. Æ POR, ResetCold, System reset, ResetCPU  
(2) External reset from PA[3/4] if software enabled  
(3) Internal reset from the Digital Watchdog.  
(4) Internal reset from the Sleep Counter Reset.  
Æ System Reset, Reset CPU  
Æ System Reset, Reset CPU  
Æ System Reset, Reset CPU  
(5) Wake-Up on change from PA[0/5] or PA[3/4] if software enabled. Æ System Reset, Reset CPU  
Table 4.1 Reset sources that can be used in different Operating modes  
Reset Sources  
ACTIVE mode  
STAND-BY mode  
SLEEP mode  
POR (static) with Power Check  
Software enabled reset on PA[3/4]  
Digital Watch-Dog Timer  
Sleep Counter Reset  
Wake Up on Change from Sleep  
Going in Sleep mode  
Yes  
Yes  
Yes  
XS dig. debounce  
XS dig. debounce  
XS analog debounce  
XS  
No  
No  
XS  
No  
No  
No  
No  
XS  
XS  
No  
YES  
XS = software enable  
Figure 6. EM6682 Reset Structure  
RESETs generation logic diagram  
SCRsel[1:0]  
Ck[1]  
NoWDtim  
WDVal0  
WDVal1  
Write - Reset  
Read Statuts  
Watchdog  
times  
typ. 100Hz  
Sleep Counter  
Reset Oscillator  
Prescaler  
Write - Active  
Read Statuts  
SleepEn  
Sleep  
Sleep  
ResetCold  
System Reset  
Delay  
ResSys  
Peripherals  
&
Analog  
CPU  
Filter  
ck[15]  
WakeUp (on  
Change)  
Debounce  
POR &  
Power-Check  
POR  
InResAH  
ck[9]  
Set  
PORstatus  
Reset  
Rd RegSysCntl1  
PA[3]  
PA[4]  
PA[3/4]Resin  
All signals enter bottom, left, top and output on the right side of the boxes  
All reset sources activate the System Reset (ResSys). The ‘System Reset Delay’ ensures that the system reset remains active  
long enough for all system functions to be reset (active for N system clock cycles. CPU is reset by the same reset  
As well as activating the system reset, the POR also resets all bits in registers marked ‘p’ and the sleep enable (SleepEn)  
latch. System reset do not reset these registers bits, nor the sleep enable latch.  
7
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Copyright © 2005, EM Microelectronic-Marin SA  

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