Datasheet > EM639165TS-6G

EM639165TS-6G

更新时间： 2024-01-24 23:36:11

品牌	Logo	应用领域
钰创 - ETRON		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
73页	1303K
描述
8Mega x 16 Synchronous DRAM (SDRAM)

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技术参数
数据手册

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EM639165TS-6G 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

EM639165TS-6G 数据手册

EtronTech

EM639165

T 1

CLK

COMMAND

READ A

NOP

DOUT A

CAS# latency=2

, DQ's

CK2

DOUT A

CAS# latency=3

, DQ's

CK3

Burst Read Operation

(Burst Length = 4, CAS# Latency = 2, 3)

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier

(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function

may be interrupted by a subsequent Read or Write command to the same bank or the other active

bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll

command to the same bank too. The interrupt coming from the Read command can occur on any

clock cycle following a previous Read command (refer to the following figure).

T 1

CLK

COMMAND

READ A

READ B

NOP

CAS# latency=2

DOUT A

DOUT B

, DQ's

CK2

CAS# latency=3

, DQ's

DOUT A

DOUT B

CK3

Read Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes

from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write

command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a

single cycle with high-impedance on the DQ pins must occur between the last read data and the

Write command (refer to the following three figures). If the data output of the burst read occurs at the

second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the

Write command to avoid internal bus contention.

CLK

DQM

COMMAND

DQ's

NOP

READ A

NOP

WRITE B

DINB

NOP

DOUT A

DINB

Must be Hi-Z before

the Write Command

: "H" or "L"

Read to Write Interval

(Burst Length ≥ 4, CAS# Latency = 3)

Rev 1.6 Feb. 2007

1...4 5 678 9 10...73

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