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EH2525TTS-58.924MTR PDF预览

EH2525TTS-58.924MTR

更新时间： 2024-11-22 08:38:23
品牌 Logo 应用领域
日蚀 - ECLIPTEK 输出元件
页数 文件大小 规格书
10页 935K
描述
CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT

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EH2525TTS-58.924MTR 数据手册

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Ecliptek | EH25 Series Oscillator  
http://www.ecliptek.com/oscillators/EH25/  
Log On | 714-433-1200 | Email Customer Support  
Home  
Products  
Quick Quote  
My Parts List  
Site Map  
Contact Us  
EH25 Series Oscillator  
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)  
2011/65 +  
168 SVHC  
2015/863  
Revision G 06/08/2012  
ectrical Specifications  
Nominal Frequency  
1.000MHz to 155.520MHz  
Some frequencies within this range may not be available.  
requency Tolerance/Stability  
(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency  
Stability over the Operating Temperature Range, Supply Voltage  
Change, Output Load Change, First Year Aging at 25°C, Shock, and  
Vibration)  
±100ppm Maximum  
±50ppm Maximum  
±25ppm Maximum  
±20ppm Maximum  
ging at 25°C  
±5ppm/year Maximum  
Operating Temperature Range  
0°C to +70°C  
-40°C to +85°C  
upply Voltage  
nput Current  
5.0V  
±10%  
DC  
No Load  
50mA Maximum  
Output Voltage Logic High (V  
)
OH  
I
= -16mA  
OH  
2.4V  
Load  
Minimum with TTL Load, V -0.4V  
DD  
Minimum with HCMOS  
DC  
DC  
Output Voltage Logic Low (V  
uty Cycle  
)
I
= +16mA  
OL  
OL  
0.4V  
Maximum with TTL Load, 0.5V  
Maximum with HCMOS Load  
DC  
DC  
50 ±10(%) Measured at 1.4V  
with TTL Load or at 50% of waveform  
DC  
with HCMOS Load from 1MHz to 70MHz Measured at 50% of waveform  
above 70MHz  
50 ±5(%) Measured at 50% of waveform  
ise Time/Fall Time  
oad Drive Capability  
Measured at 0.8V  
to 2.0V with TTL Load; Masured at 20% to 80%  
DC  
DC  
of waveform with HCMOS Load  
6nSec Maximum from 1MHz to 70MHz  
4nSec Maximum from 70.000001MHz to 155.520MHz  
10 TTL Load or 50pF HCMOS Load Maximum from 1MHz to 70MHz  
5 TTL Load or 15pF HCMOS Load Maximum from 70.000001MHz to  
155.520MHz  
Output Logic Type  
in 1 Connection  
CMOS  
Tri-State (High Impedance)  
ri-State Input Voltage (Vih and Vil)  
+2.2V  
Minimum to Enable Output, +0.8V  
Maximum to Disable  
DC  
DC  
Output (High Impedance), No Connect to Enable Output  
bsolute Clock Jitter  
±250pSec Maximum, ±100pSec Typical  
One Sigma Clock Period Jitter  
±50pSec Maximum, ±30pSec Typical  
1 of 10  
28-Jan-2016 1:03 PM  
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