Datasheet > EH2500ETTTS-39.309406M

EH2500ETTTS-39.309406M

更新时间： 2024-11-22 04:29:51

品牌	Logo	应用领域
日蚀 - ECLIPTEK		石英晶振
页数	文件大小	规格书
10页	935K
描述
CMOS, Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD) Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

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Ecliptek | EH25 Series Oscillator

http://www.ecliptek.com/oscillators/EH25/

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EH25 Series Oscillator

Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)

2011/65 +

168 SVHC

2015/863

Revision G 06/08/2012

Electrical Specifications

Nominal Frequency

1.000MHz to 155.520MHz

Some frequencies within this range may not be available.

Frequency Tolerance/Stability

(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency

Stability over the Operating Temperature Range, Supply Voltage

Change, Output Load Change, First Year Aging at 25°C, Shock, and

Vibration)

±100ppm Maximum

±50ppm Maximum

±25ppm Maximum

±20ppm Maximum

Aging at 25°C

±5ppm/year Maximum

Operating Temperature Range

0°C to +70°C

-40°C to +85°C

Supply Voltage

Input Current

5.0V

±10%

No Load

50mA Maximum

Output Voltage Logic High (V

)

= -16mA

2.4V

Load

Minimum with TTL Load, V -0.4V

Minimum with HCMOS

Output Voltage Logic Low (V

Duty Cycle

)

= +16mA

0.4V

Maximum with TTL Load, 0.5V

Maximum with HCMOS Load

50 ±10(%) Measured at 1.4V

with TTL Load or at 50% of waveform

with HCMOS Load from 1MHz to 70MHz Measured at 50% of waveform

above 70MHz

50 ±5(%) Measured at 50% of waveform

Rise Time/Fall Time

Load Drive Capability

Measured at 0.8V

to 2.0V with TTL Load; Masured at 20% to 80%

of waveform with HCMOS Load

6nSec Maximum from 1MHz to 70MHz

4nSec Maximum from 70.000001MHz to 155.520MHz

10 TTL Load or 50pF HCMOS Load Maximum from 1MHz to 70MHz

5 TTL Load or 15pF HCMOS Load Maximum from 70.000001MHz to

155.520MHz

Output Logic Type

Pin 1 Connection

CMOS

Tri-State (High Impedance)

Tri-State Input Voltage (Vih and Vil)

+2.2V

Minimum to Enable Output, +0.8V

Maximum to Disable

Output (High Impedance), No Connect to Enable Output

Absolute Clock Jitter

±250pSec Maximum, ±100pSec Typical

One Sigma Clock Period Jitter

±50pSec Maximum, ±30pSec Typical

1 of 10

28-Jan-2016 1:03 PM

12 3 4 5 6 7...10

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