EFM32JG12 Family Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFM32JG12 product family is well suited for any battery operated application as well as other systems requiring high performance
and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description can be
found in the EFM32JG12 Reference Manual.
A block diagram of the EFM32JG12 family is shown in Figure 3.1 Detailed EFM32JG12 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Port I/O Configuration
Digital Peripherals
IOVDD
Energy Management
AVDD_1
IOVDD
AVDD_0
DVDD
LETIMER
Voltage
Monitor
Port A
Drivers
PAn
TIMER
CRYOTIMER
PCNT
bypass
Port B
Drivers
PBn
PCn
PDn
PFn
VREGVDD
VREGSW
DC-DC
Voltage
Converter
Regulator
RTC / RTCC
USART
Port
Mapper
DECOUPLE
Port C
Drivers
LEUART
I2C
ARM Cortex-M3 Core
Brown Out /
Power-On
Reset
Port D
Drivers
Up to 1024 KB ISP Flash
Program Memory
CRYPTO
CRC
Reset
Management
Unit
A
H
B
A
P
B
RESETn
Port F
Drivers
Up to 256 KB RAM
Memory Protection Unit
LDMA Controller
LESENSE
Serial Wire
and ETM
Debug /
Analog Peripherals
Debug Signals
(shared w/GPIO)
Port I
Drivers
PIn
Programming
IDAC
Port J
Drivers
-
+
PJn
Watchdog
Timer
VDAC
Op-Amp
VDD
Internal
Reference
Port K
Drivers
PKn
Clock Management
ULFRCO
AUXHFRCO
LFRCO
12-bit ADC
Temp
Sense
LFXTAL_P
LFXTAL_N
HFXTAL_P
HFXTAL_N
LFXO
HFRCO + DPLL
HFXO
Capacitive
Sense
+
-
Analog Comparator
Figure 3.1. Detailed EFM32JG12 Block Diagram
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