Datasheet > EDJ8232E5MB

EDJ8232E5MB

更新时间： 2024-11-28 11:45:07

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
142页	1212K
描述
8G bits DDR3L SDRAM, DDP

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EDJ8232E5MB 数据手册

DATA SHEET

8G bits DDR3L SDRAM, DDP

EDJ8232E5MB (256M words  32 bits)

Specifications

Features

 Density: 8G bits

 Organization

 32M words  32 bits  8 banks

 Package

 Double-data-rate architecture: two data transfers per

clock cycle

 The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

 Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

 136-ball FBGA

 DDP: 2 pieces of 4G bits chip sealed in one

package

 DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

 Lead-free (RoHS compliant) and Halogen-free

 Power supply: 1.35V (typ.)

 Differential clock inputs (CK and /CK)

 VDD, VDDQ  1.283V to 1.45V

 Backward compatible for VDD, VDDQ

 1.5V  0.075V

 DLL aligns DQ and DQS transitions with CK

transitions

 Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

 Data rate

 Data mask (DM) for write data

 Posted /CAS by programmable additive latency for

better command and data bus efficiency

 1600Mbps/1333Mbps (max.)

 4KB page size

 Row address: A0 to A14

 Column address: A0 to A9

 Eight internal banks for concurrent operation

 Burst lengths (BL): 8 and 4 with Burst Chop (BC)

 Burst type (BT):

 Sequential (8, 4 with BC)

 Interleave (8, 4 with BC)

 /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

 /CAS Write Latency (CWL): 5, 6, 7, 8

 On-Die Termination (ODT) for better signal quality

 Synchronous ODT

 Dynamic ODT

 Asynchronous ODT

 Multi Purpose Register (MPR) for pre-defined pattern

read out

 ZQ calibration for DQ drive and ODT

 Programmable Partial Array Self-Refresh (PASR)

 /RESET pin for Power-up sequence and reset

function

 Precharge: auto precharge option for each burst

access

 SRT range:

 Normal/extended

 Programmable Output driver impedance control

 Driver strength: RZQ/7, RZQ/6 (RZQ = 240)

 Refresh: auto-refresh, self-refresh

 Refresh cycles

 Average refresh period

7.8s at 0C  TC  85C

3.9s at 85C  TC  95C

 Operating case temperature range

 TC = 0C to +95C

Document No. E1813E40 (Ver. 4.0)

Date Published April 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011-2012

12 3 4 5 6 7...142

中文翻译

下载PDF

与EDJ8232E5MB相关器件

型号	品牌	获取价格	描述	数据表
EDJ8232E5MB-DJ-F	ELPIDA	获取价格	8G bits DDR3L SDRAM, DDP
EDJ8232E5MB-GN-F	ELPIDA	获取价格	8G bits DDR3L SDRAM, DDP
EDK	KEMET	获取价格	Aluminum Electrolytic Capacitors
EDK104M050A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK105M025A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK105M050A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK106M016A9BAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK106M025A9DAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK106M035A9DAA	KEMET	获取价格	SMD Surface mount lead terminals â General
EDK106M050A9GAA	KEMET	获取价格	SMD Surface mount lead terminals â General

与EDJ8232E5MB相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

48
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

38
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

66
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

62

产品中心

服务支持

精选活动

关于我们

帮助中心

EDJ8232E5MB

EDJ8232E5MB 数据手册

与EDJ8232E5MB相关器件

与EDJ8232E5MB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EDJ8232E5MB

EDJ8232E5MB 数据手册

与EDJ8232E5MB相关器件

与EDJ8232E5MB相关文章

您还可以找

您在本页遇到什么问题？