Datasheet > 存储 > DRAM> EDJ1104BASE

EDJ1104BASE

更新时间： 2024-11-25 06:55:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
148页	1889K
描述
1G bits DDR3 SDRAM

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中文翻译

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数据手册

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EDJ1104BASE 数据手册

DATA SHEET

1G bits DDR3 SDRAM

EDJ1104BASE (256M words × 4 bits)

EDJ1108BASE (128M words × 8 bits)

EDJ1116BASE (64M words × 16 bits)

Features

Specifications

• Density: 1G bits

• Organization

32M words × 4 bits × 8 banks (EDJ1104BASE)

16M words × 8 bits × 8 banks (EDJ1108BASE)

8M words × 16 bits × 8 banks (EDJ1116BASE)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

78-ball FBGA (EDJ1104/1108BASE)

96-ball FBGA (EDJ1116BASE)

Lead-free (RoHS compliant)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

• Power supply: VDD, VDDQ = 1.5V ± 0.075V

• Data rate

1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)

• 1KB page size (EDJ1104/1108BASE)

Row address: A0 to A13

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

Column address: A0 to A9, A11 (EDJ1104BASE)

better command and data bus efficiency

A0 to A9 (EDJ1108BASE)

• On-Die Termination (ODT) for better signal quality

Synchronous ODT

• 2KB page size (EDJ1116BASE)

Row address: A0 to A12

Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

Sequential (8, 4 with BC)

Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

Dynamic ODT

Asynchronous ODT

• Multi Purpose Register (MPR) for temperature read

out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

• SRT range:

Normal/extended

Auto/manual self-refresh

• Programmable Output driver impedance control

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1128E60 (Ver. 6.0)

Date Published April 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2007-2009

12 3 4 5 6 7...148

中文翻译

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与EDJ1104BASE相关器件

型号	品牌	获取价格	描述	数据表
EDJ1104BASE-8A-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-8C-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-AC-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-AE-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-AG-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-DG-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BASE-DJ-E	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BBSE	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BBSE-8A-F	ELPIDA	获取价格	1G bits DDR3 SDRAM
EDJ1104BBSE-8C-F	ELPIDA	获取价格	1G bits DDR3 SDRAM

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