EDI816256CA
White Electronic Designs
256Kx16 MONOLITHIC SRAM, SMD 5962-96795
The EDI816256CAis a 4 megabit Monolithic CMOS Static
RAM.
FEATURES
ꢀ
256Kx16 bit CMOS Static
The EDI816256CA uses 16 common input and output
lines and has an output enable pin which operates faster
than address access time at read cycle. The device allows
upper and lower byte access by use of the data byte control
pins (LB#, UB#).
ꢀ
Random Access Memory
• Access Times of 17, 20, 25, 35ns
• Data Retention Function (LPA version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The devices are available in a fully hermetic 44 lead
ceramic SOJ and a 44 lead Ceramic Flatpack. The Ceramic
SOJ is pin for pin compatible with the commercially
available plastic SOJ. This allows the user the luxury of
designing a board that can be used for both the commercial
and military market.
ꢀ
ꢀ
44 lead JEDEC Approved Revolutionary Pinout
• Ceramic SOJ (Package 322)
• Ceramic Flatpack (Package 323)
Single +5V ( 10ꢀ) Supply Operation
ALow Power version with Data Retention (EDI816256LPA)
is also available for battery backed applications. Military
product is available compliant to Appendix A of MIL-PRF-
38535.
PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
A0-17
LB# (I/O1-8)
UB# (I/O9-16)
I/O1-16
CS#
Address Inputs
Lower-Byte Control (I/O1-8)
Upper-Byte Control (I/O9-16)
Data Input/Output
Chip Select
A0
A1
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A2
3
A15
A3
A4
4
5
6
OE#
UB#
LB#
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
7
8
9
I/O16
I/O15
I/O14
I/O13
VSS
OE#
Output Enable
WE#
Write Enable
10
11
12
13
14
15
16
17
18
19
20
21
22
VCC
+5.0V Power
VSS
Ground
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
NC
No Connection
A6
A7
A8
A9
A10
August 2004
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com