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EC3A-2

更新时间: 2024-11-29 06:55:35
品牌 Logo 应用领域
RCD 延迟线
页数 文件大小 规格书
1页 975K
描述
PROGRAMMABLE ECL DELAY LINES

EC3A-2 数据手册

  
RESISTORSCAPACITORSCOILSDELAY LINES  
PROGRAMMABLE ECL DELAY LINES  
Term.W is  
RoHS  
compliant  
EC3A 3 BIT 10K ECL LOGIC  
RoHS  
EC3H 3 BIT 10KH ECL LOGIC  
Incremental delays of 0.5nS to 10nS  
Choice of 16-pin DIP or SM package  
Incremental  
Delay per  
Step (nS)  
Referenced to "000" - Delay in nS per Program Setting (P3*P2*P1)  
10K ECL  
RCD P/N  
10KH ECL  
RCD P/N  
Error (Ref  
to "000")  
000  
0*  
0*  
0*  
0*  
0*  
0*  
0*  
0*  
0*  
0*  
001  
0.5  
0.75  
1.0  
1.25  
1.5  
2.0  
2.5  
3.0  
5.0  
10  
010  
1.0  
1.5  
2.0  
2.5  
3.0  
4.0  
5.0  
6.0  
10  
011  
1.5  
2.25  
3.0  
3.75  
4.5  
6.0  
7.5  
9.0  
15  
100  
2.0  
3.0  
4.0  
5.0  
6.0  
8.0  
10  
101  
2.5  
3.75  
5.0  
6.25  
7.5  
10  
110  
3.0  
4.5  
6.0  
7.5  
9.0  
12  
111  
3.5  
EC3A-0.5  
EC3A-0.75  
EC3A-1  
EC3H-0.5  
EC3H-0.75  
EC3H-1  
0.5 .25  
0.75 .3  
1.0 .4  
1.25 .5  
1.5 .5  
2.0 .7  
2.5 .7  
3.0 .7  
.30  
.50  
.50  
.70  
.70  
.80  
.90  
1.0  
1.5  
3.0  
5.25  
7.0  
EC3A-1.25  
EC3A-1.5  
EC3A-2  
EC3H-1.25  
EC3H-1.5  
EC3H-12  
EC3H-2.5  
EC3H-3  
8.75  
10.5  
14  
EC3A-2.5  
EC3A-3  
12.5  
15  
15  
17.5  
21  
12  
18  
EC3A-5  
EC3H-5  
5.0  
1
20  
25  
30  
35  
EC3A-10  
EC3H-10  
10 1.5  
20  
30  
40  
50  
60  
70  
* Inherent delay of EC3A 10K ECL is 3 ± 0.5nS and inherent delay of EC3H 10KH ECL is 1.5 ± 0.5nS. The initial delay and cumulative  
tolerances is referenced to setting “000.” For example, the setting “111” delay of EC3A-1 is 7.0 ± ±0.5 nS ref. to “000,” and 10.0 ± ±1.0 ns  
referenced to the input. The setting “111” delay of EC3H-1 is 7.0 ± ±0.5 nS ref. to “000,” and 8.5 ± ±1.0 ns referenced to the input.  
EC3A10K ECL OPERATING SPECIFICATIONS  
V
EESupply Voltage: -5.20 ± ±0.25VDC  
EE Supply Current: 60 mA typical  
.895 [22.7] Max. →  
.40 [10.2]max  
I
.295[7.5]  
max.  
SIDE VIEW  
Logic “1” Input: VIH= -.98V min., IIH= 265µA max, IIH (pin 6*)= -11mA typ.  
Logic “0” Input: VIL= -1.63V max, IIL= 0.5µA min., IIL (Pin 6*)= -2mA typ.  
.12 [3] min  
V
V
OH Logic “1” Voltage Out: -.96V min.  
OL Logic “0” Voltage Out: -1.65V max.  
±± .10 [2.54]  
.25] ±→  
.300 .01  
[7.6 .25]  
.700 .010  
[17.8  
Input Pulse Width: 40% of max. delay min.  
Operating Temp. Range: -30 to +85°C  
Storage Temperature Range: -65 to +150°C  
Type EC3A & EC3H (16-pin DIP)  
.895 [22.7] Max. →  
.285 [7.24]  
EC3H 10KH ECL OPERATING SPECIFICATIONS  
16  
1
9
8
.300  
[7.62]  
VEESupply Voltage: -5.20 ± ±0.25VDC  
EE Supply Current: 75 mA typical  
TOP VIEW  
I
.300 [7.6]  
Logic “1” Input: VIH= -.98V min., IIH= 320µA max, IIH (pin 6*)= -11mA typ.  
Logic “0” Input: VIL= -1.63V max, IIL= 0.7µA min., IIL (Pin 6*)= -2mA typ.  
.420 [10.67] max  
→ ←  
→ ←  
.10 [2.54]  
.020 [.5]  
V
V
OH Logic “1” Voltage Out: -.96V min.  
OL Logic “0” Voltage Out: -1.65V max.  
TypeEC3AG & EC3HG(16-pinSMD *)  
* Info on SM package is preliminary  
Input Pulse Width: 40% of max. delay min.  
Operating Temp. Range: -30 to +85°C  
Storage Temperature Range: -65 to +150°C  
E P1 P2 P3  
EC3A AG  
- 10 -  
B W  
P/N DESIGNATION:  
2
7
10  
9
8
6
Vee  
IN  
RCD Type: EC3A, EC3H  
OUT  
15  
Surface Mount Option: G (leave blank if  
standard thru-hole DIP)  
1,16  
Vcc  
Options: assigned by RCD (leave blank if std.)  
Delay Time (incremental delay per step)  
Packaging: B=Bulk (magazine tube std)  
CIRCUIT SCHEMATIC: ENABLE input E (pin #2) is active low.  
Output is disabled (low) when pin #2 is logic high.  
* INPUT LOADING AT PIN #6: internally connected to eight ECL  
Termination: W=Lead-free, Q=Tin/Lead  
(leave blank if either is acceptable)  
gate inputs terminated by Thevenin equivalent of 100 Ohms to -2V.  
-
-
-
RCD Components Inc, 520 E.Industrial Park Dr, Manchester, NH, USA 03109 rcdcomponents.com Tel: 603 669 0054 Fax: 603 669 5455 Email:sales@rcdcomponents.com  
-
FA112 Sale of this product is in accordance with GF-061. Specifications subject to change without notice.  

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