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EBJ21UE8BDS1-AE-F PDF预览

EBJ21UE8BDS1-AE-F

更新时间: 2024-11-21 12:20:55
品牌 Logo 应用领域
尔必达 - ELPIDA 内存集成电路光电二极管动态存储器双倍数据速率时钟
页数 文件大小 规格书
18页 196K
描述
2GB DDR3 SDRAM SO-DIMM

EBJ21UE8BDS1-AE-F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DMA包装说明:DIMM, DIMM204,24
针数:204Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84访问模式:DUAL BANK PAGE BURST
最长访问时间:0.3 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):533 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N204JESD-609代码:e4
长度:67.6 mm内存密度:34359738368 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:204字数:536870912 words
字数代码:512000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:512MX64输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM204,24封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5 V认证状态:Not Qualified
刷新周期:8192座面最大高度:3.8 mm
自我刷新:YES最大待机电流:0.208 A
子类别:DRAMs最大压摆率:2.64 mA
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:0.6 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:30 mmBase Number Matches:1

EBJ21UE8BDS1-AE-F 数据手册

 浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第2页浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第3页浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第4页浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第5页浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第6页浏览型号EBJ21UE8BDS1-AE-F的Datasheet PDF文件第7页 
DATA SHEET  
2GB DDR3 SDRAM SO-DIMM  
EBJ21UE8BDS1 (256M words × 64 bits, 2 Ranks)  
Specifications  
Features  
Density: 2GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
256M words × 64 bits, 2 ranks  
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 204-pin socket type small outline dual in  
line memory module (SO-DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD = 1.5V ± 0.075V  
Data rate: 1333Mbps/1066Mbps (max.)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Eight internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Interface: SSTL_15  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
/CAS Latency (CL): 5, 6, 7, 8, 9  
/CAS write latency (CWL): 5, 6, 7  
On-Die-Termination (ODT) for better signal quality  
Synchronous ODT  
Dynamic ODT  
Precharge: auto precharge option for each burst  
access  
Asynchronous ODT  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
Multi Purpose Register (MPR) for temperature read  
out  
ZQ calibration for DQ drive and ODT  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Programmable Partial Array Self-Refresh (PASR)  
/RESET pin for Power-up sequence and reset  
Operating case temperature range  
TC = 0°C to +95°C  
function  
SRT range:  
Normal/extended  
Programmable Output driver impedance control  
Document No. E1623E20 (Ver. 2.0)  
Date Published April 2010 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2010  

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