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EBD26UC6AKSA-7A-E PDF预览

EBD26UC6AKSA-7A-E

更新时间: 2024-02-13 23:01:36
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
19页 210K
描述
256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)

EBD26UC6AKSA-7A-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SODIMM包装说明:DIMM, DIMM200,24
针数:200Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:0.75 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XZMA-N200
内存密度:2147483648 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:200
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM200,24
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:2.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.048 A
子类别:DRAMs最大压摆率:2.8 mA
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:0.6 mm
端子位置:ZIG-ZAG处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBD26UC6AKSA-7A-E 数据手册

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EBD26UC6AKSA-E  
Electrical Specifications  
All voltages are referenced to VSS (GND).  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
V
Note  
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
–1.0 to +3.6  
–1.0 to +3.6  
50  
VDD  
IO  
V
mA  
W
PD  
8
Operating ambient temperature  
Storage temperature  
TA  
0 to +70  
–55 to +125  
°C  
°C  
1
Tstg  
Note: 1. DDR SDRAM component specification.  
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Compoment Specification)  
Parameter  
Symbol  
VDD, VDDQ  
VSS  
min.  
typ.  
2.5  
0
max.  
2.7  
0
Unit  
V
Notes  
1
Supply voltage  
2.3  
0
V
Input reference voltage  
Termination voltage  
Input high voltage  
Input low voltage  
VREF  
0.49 × VDDQ  
VREF – 0.04  
VREF + 0.15  
–0.3  
0.50 × VDDQ 0.51 × VDDQ  
V
VTT  
VREF  
VREF + 0.04  
VDDQ + 0.3  
VREF – 0.15  
V
VIH (DC)  
VIL (DC)  
V
2
3
V
Input voltage level,  
VIN (DC)  
VIX (DC)  
VID (DC)  
–0.3  
VDDQ + 0.3  
V
V
V
4
CK and /CK inputs  
Input differential cross point  
voltage, CK and /CK inputs  
Input differential voltage,  
CK and /CK inputs  
0.5 × VDDQ 0.2V 0.5 × VDDQ  
0.36  
0.5 × VDDQ + 0.2V  
VDDQ + 0.6  
5, 6  
Notes: 1. VDDQ must be lower than or equal to VDD.  
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.  
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.  
4. VIN (DC) specifies the allowable DC execution of each differential input.  
5. VID (DC) specifies the input differential voltage required for switching.  
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V  
if measurement.  
Preliminary Data Sheet E0605E10 (Ver. 1.0)  
10  

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