Datasheet > EBD11UD8ADFB-6B-E

EBD11UD8ADFB-6B-E

更新时间： 2024-02-19 05:51:42

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
19页	187K
描述
DDR DRAM Module, 128MX64, 0.7ns, CMOS, DIMM-184

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

EBD11UD8ADFB-6B-E 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIMM	包装说明：	DIMM,
针数：	184	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.36
风险等级：	5.84	访问模式：	DUAL BANK PAGE BURST
最长访问时间：	0.7 ns	其他特性：	AUTO/SELF REFRESH
JESD-30 代码：	R-XDMA-N184	JESD-609代码：	e4
内存密度：	8589934592 bit	内存集成电路类型：	DDR DRAM MODULE
内存宽度：	64	功能数量：	1
端口数量：	1	端子数量：	184
字数：	134217728 words	字数代码：	128000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128MX64
封装主体材料：	UNSPECIFIED	封装代码：	DIMM
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
自我刷新：	YES	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Gold (Au)
端子形式：	NO LEAD	端子位置：	DUAL
处于峰值回流温度下的最长时间：	50	Base Number Matches：	1

EBD11UD8ADFB-6B-E 数据手册

浏览型号EBD11UD8ADFB-6B-E的Datasheet PDF文件第10页

浏览型号EBD11UD8ADFB-6B-E的Datasheet PDF文件第11页

浏览型号EBD11UD8ADFB-6B-E的Datasheet PDF文件第12页

浏览型号EBD11UD8ADFB-6B-E的Datasheet PDF文件第14页

浏览型号EBD11UD8ADFB-6B-E的Datasheet PDF文件第15页

EBD11UD8ADFB

-6B

-7A

min.

-7B

min.

Parameter

Symbol min.

max.

—

max.

—

max.

—

Unit Notes

Active to Read/Write delay tRCD

Precharge to active

tRP

—

command period

Active to auto precharge

delay

tRAP

tRCD min.

Active to active command

tRRD

—

period

Write recovery time

Auto precharge write

recovery and precharge time

tWR

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

(tWR/tCK)+

(tRP/tCK)

tDAL

tCK 13

Internal write to Read

tWTR

tREF

—

tCK

µs

command delay

Average periodic refresh

interval

—

7.8

—

7.8

—

7.8

Notes: 1. All the AC parameters listed in this data sheet is component specifications. For AC testing conditions,

refer to the corresponding component data sheet.

2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal

transition is defined to occur when the signal level crossing VTT.

3. The timing reference level is VTT.

4. Output valid window is defined to be the period between two successive transition of data out or DQS

(read) signals. The signal transition is defined to occur when the signal level crossing VTT.

5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The

timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage

level, but specify when the device output stops driving.

6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This

parameter is not referred to a specific DOUT voltage level, but specify when the device output begins

driving.

7. Input valid windows is defined to be the period between two successive transition of data input or DQS

(write) signals. The signal transition is defined to occur when the signal level crossing VREF.

8. The timing reference level is VREF.

9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific

reference voltage to judge this transition is not given.

10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not

assured.

11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these

values are 10% of tCK.

12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than

0.4V/400 cycle.

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,

tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)

tDAL = 5 clocks

Data Sheet E0414E20 (Ver. 2.0)

1...10 11 121314 15 16...19

下载PDF

与EBD11UD8ADFB-6B-E相关器件

型号	品牌	描述	获取价格	数据表
EBD11UD8ADFB-7A	ELPIDA	1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)	获取价格
EBD11UD8ADFB-7A-E	ELPIDA	暂无描述	获取价格
EBD11UD8ADFB-7B	ELPIDA	1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)	获取价格
EBD12RB8ALFA	ELPIDA	128MB Registered DDR SDRAM DIMM	获取价格
EBD12RB8ALFA-1A	ELPIDA	128MB Registered DDR SDRAM DIMM	获取价格
EBD12RB8ALFA-75	ELPIDA	128MB Registered DDR SDRAM DIMM	获取价格

与EBD11UD8ADFB-6B-E相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

3
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

5
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

3
资料手册解读：UC3842参数和管脚说明
2024-05-22

5

产品中心

服务支持

精选活动

关于我们

帮助中心

EBD11UD8ADFB-6B-E

EBD11UD8ADFB-6B-E 技术参数

EBD11UD8ADFB-6B-E 数据手册

与EBD11UD8ADFB-6B-E相关器件

与EBD11UD8ADFB-6B-E相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EBD11UD8ADFB-6B-E

EBD11UD8ADFB-6B-E 技术参数

EBD11UD8ADFB-6B-E 数据手册

与EBD11UD8ADFB-6B-E相关器件

与EBD11UD8ADFB-6B-E相关文章

您还可以找

您在本页遇到什么问题？