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EB201

更新时间: 2024-02-26 03:26:25
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安森美 - ONSEMI /
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8页 122K
描述
High Cell Density MOSFETs Low On-Resistance Affords New Design Options

EB201 数据手册

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EB201/D  
High Cell Density MOSFETs  
Low On–Resistance Affords  
New Design Options  
Prepared by: Kim Gauen and Wayne Chavez  
ON Semiconductor  
http://onsemi.com  
ENGINEERING BULLETIN  
Just a few years ago an affordable 60 V, 10 mpower  
transistor was a dream. After all, 10 mis the resistance of  
on–resistance are its spreading, channel, JFET,  
accumulation region, and substrate resistances. To achieve  
about 20 cm of #22 gauge wire. Today a sub–10 mpower  
MOSFET is not only available, it is housed in a standard  
TO–220. Such are the advances that have occurred lately in  
“high cell density” power MOSFET technology.  
Furthermore, Motorola’s high cell density technology,  
HDTMOS , brings other advantages such as greatly  
improved body diode performance. The technological  
advances are sufficiently great that they are fundamentally  
changing low voltage power transistor technology.  
ultra–low R  
, device designers must decrease the  
DS(on)  
resistance of all these components. Most of the resistive  
elements can be reduced by shrinking cell size and adding  
more cells per square centimeter of silicon. However, there  
is a limit to maximum packing density. As cell density  
becomes very high, on–resistance actually increases due to  
a higher JFET resistance. With today’s processes and cell  
geometries, the optimum cell density is about five times that  
of standard power MOSFETs. Devices built with ON  
Semiconductor’s high cell density process (HDTMOS)  
2
2
Cutting the MOSFET’s On–Resistance  
A cross section of the power MOSFET is shown in  
Figure 1. The major contributors to the standard MOSFET’s  
employ about 6 M cells/in , up from the 1.2 M cells/in used  
in standard power MOSFETs. Figure 2 illustrates the  
marked difference in cell density.  
SOURCE  
SOURCE  
GATE  
R (PACKAGE)  
R (METAL)  
R (CONTACT)  
P +  
P +  
R (CH)  
P –  
R (JFET)  
R(N+)  
R (ACCUM)  
N
epi  
R (SPREAD)  
R (BULK)  
R (SUBSTRATE)  
DRAIN  
N + SUBSTRATE  
Figure 1. HDTMOS Cross Section  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
February, 2002 – Rev. 1  
EB201/D  

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