Datasheet > DSP56F801

DSP56F801

更新时间： 2024-01-25 04:55:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		数字信号处理器
页数	文件大小	规格书
40页	345K
描述
16-bit Digital Signal Processor

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中文翻译

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数据手册

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DSP56F801 数据手册

DSP56F801/D

Rev. 7.0, 1/2002

DSP56F801

Preliminary Technical Data

DSP56F801 16-bit Digital Signal Processor

•

Up to 40 MIPS operation at 80 MHz core

frequency

•

Hardware DO and REP loops

6-channel PWM Module

DSP and MCU functionality in a unified,

C-efficient architecture

Two 4-channel, 12-bit ADCs

Serial Communications Interface (SCI)

Serial Peripheral Interface (SPI)

General Purpose Quad Timer

JTAG/OnCE^TMport for debugging

On-chip relaxation oscillator

11 shared GPIO

MCU-friendly instruction set supports both

DSP and controller functions: MAC, bit

manipulation unit, 14 addressing modes

•

8K × 16-bit words Program Flash

1K × 16-bit words Program RAM

2K × 16-bit words Data Flash

1K × 16-bit words Data RAM

2K × 16-bit words Boot Flash

48-pin LQFP Package

PWM Outputs

PWMA

RESET

Fault Input

VCAPC

SSA

DDA

IRQA

Digital Reg

JTAG/

OnCE

Port

Analog Reg

Low Voltage

Supervisor

A/D1

A/D2

ADC

VREF

Interrupt

Controller

Data ALU

Address

Generation

Unit

Bit

Manipulation

Unit

Program Controller

and

Hardware Looping Unit

16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Program Memory

8188 x 16 Flash

1024 x 16 SRAM

PAB

PLL

•

PDB

Quad Timer C

16-Bit

DSP56800

Core

•

Clock Gen

or Optional

Internal

GPIOB3/XTAL

Quad Timer D

or GPIO

Boot Flash

2048 x 16 Flash

GPIOB2/EXTAL

XDB2

Relaxation Osc.

CGDB

Data Memory

2048 x 16 Flash

1024 x 16 SRAM

•

XAB1

XAB2

•

INTERRUPT

CONTROLS

IPBB

CONTROLS

SCI0

GPIO

COP/

Watchdog

COP RESET

MODULE CONTROLS

Application-

Specific

Memory &

Peripherals

IPBus Bridge

(IPBB)

SPI

GPIO

ADDRESS BUS [8:0]

DATA BUS [15:0]

*includes TCS pin which is reserved for factory use and is tied to VSS

Figure 1. DSP56F801 Block Diagram

12 3 4 5 6 7...40

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