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DSKTJ04T

更新时间: 2024-09-25 18:22:47
品牌 Logo 应用领域
松下 - PANASONIC /
页数 文件大小 规格书
4页 364K
描述
Small Signal Field-Effect Transistor, N-Channel, Junction FET

DSKTJ04T 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
风险等级:5.65FET 技术:JUNCTION
最高工作温度:80 °C极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):0.1 W子类别:Other Transistors
表面贴装:YESBase Number Matches:1

DSKTJ04T 数据手册

 浏览型号DSKTJ04T的Datasheet PDF文件第2页浏览型号DSKTJ04T的Datasheet PDF文件第3页浏览型号DSKTJ04T的Datasheet PDF文件第4页 
This product complies with the RoHS Directive (EU 2002/95/EC).  
DSKTJ04  
Silicon N-channel Junction FET  
For impedance conversion in low frequency  
Package  
Features  
Code  
Low noise voltage NV and high speed stability time  
Contributes to miniaturization of sets, reduction of component count.  
Eco-friendly Halogen-free package  
TSSSMini3-F2-B  
Pin Name  
1: Drain  
Packaging  
2: Source  
Embossed type (Thermo-compression sealing): 10000 pcs / reel (standard)  
3: Gate  
Absolute Maximum Ratings Ta = 25°C  
Marking Symbol: 8  
Parameter  
Drain-source voltage (Gate open)  
Drain-gate voltage (Souece open)  
Drain-source current (Gate open)  
Drain-gate current (Souece open)  
Power dissipation  
Symbol  
VDSO  
VDGO  
IDSO  
Rating  
Unit  
V
20  
20  
V
2
2
mA  
mA  
mW  
°C  
IDGO  
PD  
100  
Operating ambient temperature  
Storage temperature  
Topr  
–20 to +80  
–55 to +150  
T
°C  
stg  
Electrical Characteristics Ta = 25°C±3°C  
Parameter  
1
Symbol  
Conditions  
Min  
100  
110  
660  
Typ  
Max  
470  
460  
Unit  
mA  
mA  
mS  
Drain current*  
ID  
VDS = 2.0 V, Rd = 2.2 kW ± 1%  
2
Drain-source cutoff current *  
IDSS  
VDS = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0  
VD = 2.0 V, VGS = 0, f = 1 MHz  
Forward transfer admittance  
1500  
Yfs  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, A-curve  
3
Noise voltage *  
NV  
GV1  
4
mV  
dB  
dB  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
–5.0  
–7.0  
–1.0  
–1.5  
0
VD = 1.5 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
Voltage gain  
GV2  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz to 70 Hz  
4
ΔGV . f*  
1.7  
2.0  
dB  
dB  
Voltage gain difference  
0
GV1 – GV2  
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.  
2. A protection diode is built-in between gate and source of transistor. However if forward current ows between gate and source transistor  
might be damaged. So please be careful not insert reverse.  
3. 1: ID is assured for IDSS .  
*
2: Rank classication  
*
Code  
S
S
T
T
U
U
Rank  
ID (mA)  
100 to 220  
110 to 210  
8S  
180 to 320  
190 to 310  
8T  
280 to 470  
290 to 460  
8U  
IDSS (mA)  
Marking Symbol  
3: NV is assured for design.  
*
*
4: ΔG . fis assured for AQL 0.065%. (The measurement method is used by source-grounded circuit.)  
V
Publication date: December 2011  
Ver. AED  
1

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