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DSKTJ07U0L PDF预览

DSKTJ07U0L

更新时间： 2024-09-24 20:58:39
品牌 Logo 应用领域
松下 - PANASONIC 开关光电二极管晶体管
页数 文件大小 规格书
4页 521K
描述
Small Signal Field-Effect Transistor, 0.00047A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, SC-105AB, 3 PIN

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中文翻译

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DSKTJ07U0L 技术参数

是否Rohs认证： 符合生命周期：Not Recommended
包装说明：SC-105AB, 3 PINReach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8541.21.00.95
风险等级：5.67其他特性：LOW NOISE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：20 V
最大漏极电流 (ID)：0.00047 AFET 技术：JUNCTION
JESD-30 代码：R-PDSO-F3元件数量：1
端子数量：3工作模式：DEPLETION MODE
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL表面贴装：YES
端子形式：FLAT端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

DSKTJ07U0L 数据手册

 浏览型号DSKTJ07U0L的Datasheet PDF文件第2页浏览型号DSKTJ07U0L的Datasheet PDF文件第3页浏览型号DSKTJ07U0L的Datasheet PDF文件第4页 
DSKTJ07  
Silicon N-channel Junction FET  
For impedance conversion in low frequency  
Unit: mm  
Features  
Low noise voltage NV  
Halogen-free / RoHS compliant  
(EU RoHS / UL-94 V-0 / MSL: Level 1 compliant)  
Marking Symbol: B  
Packaging  
DSKTJ07×0L Embossed type (Thermo-compression sealing): 10000 pcs / reel (standard)  
Absolute Maximum Ratings Ta = 25°C  
Parameter  
Drain-source voltage (Gate open)  
Drain-gate voltage (Souece open)  
Drain-source current (Gate open)  
Drain-gate current (Souece open)  
Power dissipation  
Symbol  
VDSO  
VDGO  
IDSO  
Rating  
Unit  
V
20  
20  
V
1: Drain  
2: Source  
3: Gate  
2
2
mA  
mA  
mW  
°C  
IDGO  
PD  
Panasonic  
TSSSMini3-F2-B  
100  
JEITA  
Code  
SC-105AB  
Operating ambient temperature  
Storage temperature  
Topr  
–20 to +80  
–55 to +150  
T
stg  
°C  
Electrical Characteristics Ta = 25°C±3°C  
Parameter  
1
Symbol  
Conditions  
Min  
Typ  
Max  
470  
460  
Unit  
mA  
mA  
mS  
Drain current*  
ID  
VDS = 2.0 V, Rd = 2.2 kW ± 1%  
180  
190  
660  
2
Drain-source cutoff current *  
IDSS  
VDS = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0  
VD = 2.0 V, VGS = 0, f = 1 MHz  
Forward transfer admittance  
1500  
Yfs  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, A-curve  
3
Noise voltage *  
NV  
GV1  
4
mV  
dB  
dB  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
–5.0  
–7.0  
–1.0  
–1.5  
0
VD = 1.5 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
Voltage gain  
GV2  
VD = 2.0 V, Rd = 2.2 kW ± 1%,  
CO = 5 pF, eG = 10 mV, f = 1 kHz to 70 Hz  
4
ΔGV . f*  
1.7  
2.0  
dB  
dB  
Voltage gain difference  
0
GV1 – GV2  
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.  
2. A protection diode is built-in between gate and source of transistor. However if forward current flows between gate and source transistor  
might be damaged. So please be careful not insert reverse.  
3. 1: ID is assured for IDSS .  
*
2: Rank classification  
*
Code  
T
T
U
U
Rank  
ID (mA)  
180 to 320  
190 to 310  
BT  
280 to 470  
290 to 460  
BU  
IDSS (mA)  
Marking Symbol  
3: NV is assured for design.  
*
*
4: ΔG . fis assured for AQL 0.065%. (The measurement method is used by source-grounded circuit.)  
V
Publication date: August 2013  
Ver. BED  
1
1234

中文翻译

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