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DSC512-052412KE1T PDF预览

DSC512-052412KE1T

更新时间: 2024-11-27 18:40:47
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟外围集成电路
页数 文件大小 规格书
10页 672K
描述
OTHER CLOCK GENERATOR

DSC512-052412KE1T 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.63Is Samacsys:N
其他特性:CLK/CRYSTAL FREQ-NOM IS REPLACED WITH MEMS INTERNAL CLOCKJESD-30 代码:R-XQCC-N32
长度:5 mm湿度敏感等级:1
端子数量:32最高工作温度:70 °C
最低工作温度:-20 °C最大输出时钟频率:460 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260筛选级别:AEC-Q100
座面最大高度:0.9 mm最大供电电压:3.6 V
最小供电电压:2.25 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:3.2 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

DSC512-052412KE1T 数据手册

 浏览型号DSC512-052412KE1T的Datasheet PDF文件第2页浏览型号DSC512-052412KE1T的Datasheet PDF文件第3页浏览型号DSC512-052412KE1T的Datasheet PDF文件第4页浏览型号DSC512-052412KE1T的Datasheet PDF文件第5页浏览型号DSC512-052412KE1T的Datasheet PDF文件第6页浏览型号DSC512-052412KE1T的Datasheet PDF文件第7页 
DSC512-05  
Crystal-lessFour Output Clock Generator  
General Description  
Features  
The DSC512-05 is a Crystal-less, four  
output clock generator that implements  
Discera’s proven PureSiliconMEMS  
technology. The device provides excellent  
jitter and stability over a wide range of  
Two 50MHz (LVDS) Clocks  
One 14MHz (LVCMOS) Clock  
One 16MHz (LVCMOS) Clock  
supply voltages and temperatures.  
eliminating the external quartz crystal,  
MEMS clock generators significantly  
By  
Available Format on Any Output:  
o HCSL, LVPECL, LVDS or LVCMOS  
enhance reliability and accelerate product  
development, while meeting stringent clock  
performance criteria for a variety of  
communications, storage, and networking  
applications.  
Wide Temperature Range  
o Ext. Industrial: -40° to 105° C  
o Industrial: -40° to 85° C  
o Ext. commercial: -20° to 70° C  
Supply Range of 2.25 to 3.6 V  
DSC512-05 has an Output Enable / Disable  
feature allowing it to disable all outputs  
when OE1 and OE2 are low. Each output  
enable pin controls one of the two banks of  
synchronous clocks. See the OE function  
Low Power Consumption  
o 30% lower than competing devices  
Excellent Shock & Vibration Immunity  
o Qualified to MIL-STD-883  
table 1 for more detail.  
The device is  
available in a 20 pin QFN. Additional output  
formats are in any combination of LVPECL,  
LVDS, LVCMOS and HCSL.  
Available Footprints:  
o 20 QFN  
Lead Free & RoHS Compliant  
Block Diagram*  
Short Lead Time: 2 Weeks  
AEC-Q100 Automotive Qualified  
Applications  
Communications/Networking  
Embedded and Industrial  
Consumer and computation  
Medical, Military, Avionics  
Storage and enterprise  
* In the above block diagram:  
Clk0+ is 14MHz LVCMOS (Clk0- is off)  
Clk1+/- and Clk2 +/- are 50MHz LVDS;  
Clk3 + is 16MHz LVCMOS (Clk3- is off)  
For other frequencies, please contact the factor: Sales@discera.com  
______________________________________________________________________________________________________________________________________________  
DSC512-05  
Page 1  

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