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DS90CR564 PDF预览

DS90CR564

更新时间: 2024-11-22 23:49:03
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DS90CR564 数据手册

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July 1997  
DS90CR563/DS90CR564  
LVDS 18-Bit Color Flat Panel Display (FPD) Link—  
65 MHz  
General Description  
Features  
n 20 to 65 MHz shift clk support  
n Up to 171 Mbytes/s bandwidth  
n Cable size is reduced to save cost  
n 290 mV swing LVDS devices for low EMI  
The DS90CR563 transmitter converts 21 bits of CMOS/TTL  
data into three LVDS (Low Voltage Differential Signaling)  
data streams. A phase-locked transmit clock is transmitted in  
parallel with the data streams over a fourth LVDS link. Every  
cycle of the transmit clock 21 bits of input data are sampled  
and transmitted. The DS90CR564 receiver converts the  
LVDS data streams back into 21 bits of CMOS/TTL data. At  
a transmit clock frequency of 65 MHz, 18 bits of RGB data  
<
n Low power CMOS design ( 550 mW typ)  
n Power-down mode saves power ( 0.25 mW)  
<
n PLL requires no external components  
n Low profile 48-lead TSSOP package  
n Rising edge data strobe  
n Compatible with TIA/EIA-644 LVDS standard  
n Single pixel per clock XGA (1024 x 768)  
n Supports VGA, SVGA, XGA and higher  
n 1.3 Gbps throughput  
and  
3 bits of LCD timing and control data (FPLINE,  
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per  
LVDS data channel. Using a 65 MHz clock, the data through-  
put is 171 Mbytes per second. These devices are offered  
with rising edge data strobes for convenient interface with a  
variety of graphics and LCD panel controllers.  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
Block Diagrams  
DS90CR563  
DS90CR564  
DS012617-2  
DS012617-1  
Order Number DS90CR563MTD  
See NS Package Number MTD48  
Order Number DS90CR564MTD  
See NS Package Number MTD48  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS012617  
www.national.com  

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