DS89C386
www.ti.com
SNLS100C –MAY 1995–REVISED APRIL 2013
DS89C386 Twelve Channel CMOS Differential Line Receiver
Check for Samples: DS89C386
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FEATURES
DESCRIPTION
The DS89C386 is a high speed twelve channel
CMOS differential receiver that meets the
requirements of TIA/EIA-422-B. The DS89C386
features low power dissipation of 240 mW typical.
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•
•
•
•
Low Power Design—240 mW Typical
Meets TIA/EIA-422-B (RS-422)
Receiver OPEN Input Failsafe Feature
Ensured AC Parameters:
Each TRI-STATE enable, EN, allows the receiver
output to be active or in a Hi-impedance off state.
Each enable is common to only two receivers for
flexibility and multiplexing of receiver outputs.
–
–
Maximum Receiver Skew −4 ns
Maximum Transition Time −9 ns
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High Output Drive Capability: ±6 mA
Available in SSOP Packaging:
The receiver output (RO) is ensured to be High when
the inputs are left open and unterminated. The
receiver can detect signals as low and including ±200
mV over the common mode range of ±7V. The
receiver outputs (RO) are compatible with both TTL
and CMOS levels.
–
Requires 30% less PCB Space than 3
DS34C86TMs
Connection Diagrams
1/6 of package
Figure 2. Function Diagram
(1)
Truth Table
Enable
Inputs
Output
EN
L
RI–RI*
RO
Z
X
(1)
H
≥200 mV or OPEN
≤ −200 mV
H
H
L
H
+200 mV > and > −200 mV
X
Figure 1. 48-Pin SSOP
See Package Number DL0048A
(1) Not terminated.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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