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DS80C320 PDF预览

DS80C320

更新时间: 2024-01-16 16:32:12
品牌 Logo 应用领域
美信 - MAXIM 微控制器
页数 文件大小 规格书
40页 844K
描述
High-Speed/Low-Power Microcontrollers

DS80C320 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ,针数:44
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01Factory Lead Time:10 weeks
风险等级:5.12Is Samacsys:N
具有ADC:NO地址总线宽度:16
位大小:8最大时钟频率:33 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.585 mm
湿度敏感等级:3I/O 线路数量:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260认证状态:Not Qualified
ROM可编程性:MROM座面最大高度:4.572 mm
速度:33 MHz最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:16.585 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

DS80C320 数据手册

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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers  
PIN DESCRIPTION (continued)  
PIN  
NAME  
FUNCTION  
DIP  
21  
22  
23  
24  
25  
26  
27  
PLCC TQFP  
24  
25  
26  
27  
28  
29  
30  
18  
19  
20  
21  
22  
23  
24  
A8 (P2.0)  
A9 (P2.1)  
Port 2, Output. Port 2 serves as the MSB for external addressing.  
P2.7 is A15 and P2.0 is A8. The device will automatically place the  
A10 (P2.2) MSB of an address on P2 for external ROM and RAM access.  
Although Port 2 can be accessed like an ordinary I/O port, the value  
stored on the Port 2 latch will never be seen on the pins (due to  
memory access). Therefore, writing to Port 2 in software is only  
useful for the instructions MOVX A, @Ri or MOVX @Ri, A. These  
instructions use the Port 2 internal latch to supply the external address  
MSB. In this case, the Port 2 latch value will be supplied as the  
address information.  
A11 (P2.3)  
A12 (P2.4)  
A13 (P2.5)  
A14 (P2.6)  
28  
31  
25  
A15 (P2.7)  
Port 3, Input/Output. Port 3 functions as both an 8-bit, bidirectional  
I/O port and an alternate functional interface for External Interrupts,  
Serial Port 0, Timer 0 & 1 Inputs, RD and WR strobes. The reset  
condition of Port 3 is with all bits at logic 1. In this state, a weak  
pullup holds the port high. This condition also serves as an input  
mode, since any external circuit that writes to the port will overcome  
the weak pullup. When software writes a 0 to any port pin, the device  
will activate a strong pulldown that remains on until either a 1 is  
written or a reset occurs. Writing a 1 after the port has been at 0 will  
cause a strong transition driver to turn on, followed by a weaker  
sustaining pullup. Once the momentary strong driver turns off, the  
port once again becomes both the output high and input state. The  
alternate modes of Port 3 are outlined below:  
PIN  
PORT ALTERNATE  
MODE  
DIP  
PLCC TQFP  
11, 13–  
19  
10–17  
5, 7–13 P3.0–P3.7  
10  
11  
13  
14  
15  
16  
17  
18  
19  
5
7
P3.0  
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
RXD0  
TXD0  
Serial Port 0 Input  
11  
12  
13  
14  
15  
16  
17  
Serial Port 0 Output  
External Interrupt 0  
External Interrupt 1  
Timer 0 External Input  
Timer 1 External Input  
8
INT0  
INT1  
T0  
9
10  
11  
12  
13  
T1  
External Data Memory Write  
Strobe  
External Data Memory Read  
WR  
RD  
Strobe  
External Access, Active-Low Input. This pin must be connected to  
31  
35  
29  
EA  
ground for proper operation.  
No Connection (Reserved). These pins should not be connected.  
12, 34,  
1*  
6, 28,  
39*  
They are reserved for use with future devices in this family.  
N.C.  
*These pins are reserved for additional ground pins on future products.  
5 of 40  

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