DS3181/DS3182/DS3183/DS3184
Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing........................................... 86
Figure 8-40. 16-Bit Mode Write.................................................................................................................................. 87
Figure 8-41. 16-Bit Mode Read ................................................................................................................................. 87
Figure 8-42. 8-Bit Mode Write.................................................................................................................................... 88
Figure 8-43. 8-Bit Mode Read ................................................................................................................................... 88
Figure 8-44. 16-Bit Mode without Byte Swap ............................................................................................................ 89
Figure 8-45. 16-Bit Mode with Byte Swap ................................................................................................................. 89
Figure 8-46. Clear Status Latched Register on Read................................................................................................ 90
Figure 8-47. Clear Status Latched Register on Write................................................................................................ 90
Figure 8-48. RDY Signal Functional Timing Writes................................................................................................... 90
Figure 8-49. RDY Signal Functional Timing Read..................................................................................................... 91
Figure 10-1. Interrupt Structure ................................................................................................................................. 98
Figure 10-2. Internal TX Clock................................................................................................................................. 101
Figure 10-3. Internal RX Clock ................................................................................................................................ 102
Figure 10-4. Example IO Pin Clock Muxing............................................................................................................. 106
Figure 10-5. Reset Sources..................................................................................................................................... 107
Figure 10-6. CLAD Block......................................................................................................................................... 110
Figure 10-7. 8KREF Logic ....................................................................................................................................... 112
Figure 10-8. Performance Monitor Update Logic .................................................................................................... 115
Figure 10-9. Transmit Error Insert Logic.................................................................................................................. 116
Figure 10-10. Loopback Modes............................................................................................................................... 117
Figure 10-11. ALB Mux............................................................................................................................................ 117
Figure 10-12. AIS Signal Flow................................................................................................................................. 120
Figure 10-13. DS3 C-Bit or DS3 M23 (with C-Bit Generation) Frame..................................................................... 128
Figure 10-14. DS3 PLCP Frame.............................................................................................................................. 129
Figure 10-15. DS3 M23 (with C-Bits Used as Payload) Frame............................................................................... 130
Figure 10-16. E3 G.751 Frame................................................................................................................................ 130
Figure 10-17. E3 PLCP Frame ................................................................................................................................ 131
Figure 10-18. Example E3 G.751 Internal Fractional Frame................................................................................... 131
Figure 10-19. E3 G.832 Frame................................................................................................................................ 132
Figure 10-20. System Interface Functional Diagram............................................................................................... 134
Figure 10-21. Normal Packet Format in 32-Bit Mode.............................................................................................. 135
Figure 10-22. Normal Packet Format in 16-Bit Mode.............................................................................................. 135
Figure 10-23. Byte Reordered Packet Format in 32-Bit Mode ................................................................................ 135
Figure 10-24. Byte Reordered Packet Format in 16-Bit Mode ................................................................................ 136
Figure 10-25. ATM Cell/HDLC Packet Functional Diagram .................................................................................... 139
Figure 10-26. Receive DSS Scrambler Synchronization State Diagram................................................................. 143
Figure 10-27. Cell Delineation State Diagram......................................................................................................... 144
Figure 10-28. HEC Error Monitoring State Diagram................................................................................................ 145
Figure 10-29. Cell Format for 53-Byte Cell With 32-Bit Data Bus ........................................................................... 145
Figure 10-30. Cell Format for 52-Byte Cell With 32-Bit Data Bus ........................................................................... 146
Figure 10-31. PLCP Framer Functional Diagram.................................................................................................... 150
Figure 10-32. DS3 PLCP Frame Format................................................................................................................. 152
Figure 10-33. DS3 PLCP G1 Byte Format .............................................................................................................. 152
Figure 10-34. E3 PLCP Frame Format.................................................................................................................... 156
Figure 10-35. E3 PLCP G1 Byte Format................................................................................................................. 156
Figure 10-36. Fractional Payload Controller Detailed Block Diagram..................................................................... 160
Figure 10-37. Data Group Format ........................................................................................................................... 162
Figure 10-38. Frame Format.................................................................................................................................... 162
Figure 10-39. Framer Detailed Block Diagram........................................................................................................ 163
Figure 10-40. DS3 Frame Format............................................................................................................................ 165
Figure 10-41. DS3 Sub-Frame Framer State Diagram............................................................................................ 166
Figure 10-42. DS3 Multiframe Framer State Diagram............................................................................................. 167
Figure 10-43. G.751 E3 Frame Format ................................................................................................................... 174
Figure 10-44. G.832 E3 Frame Format ................................................................................................................... 176
Figure 10-45. MA Byte Format ................................................................................................................................ 177
Figure 10-46. HDLC Controller Block Diagram ....................................................................................................... 182
Figure 10-47. Trail Trace Controller Block Diagram................................................................................................ 185
Figure 10-48. Trail Trace Byte (DT = Trail Trace Data)........................................................................................... 187
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