DS3181/DS3182/DS3183/DS3184
10.14.2 Features............................................................................................................................................. 190
10.14.3 B3ZS/HDB3 Encoder ......................................................................................................................... 190
10.14.4 Transmit Line Interface ...................................................................................................................... 191
10.14.5 Receive Line Interface ....................................................................................................................... 191
10.14.6 B3ZS/HDB3 Decoder......................................................................................................................... 191
10.15BERT.........................................................................................................................................193
10.15.1 General Description ........................................................................................................................... 193
10.15.2 Features............................................................................................................................................. 193
10.15.3 Configuration and Monitoring............................................................................................................. 193
10.15.4 Receive Pattern Detection ................................................................................................................. 194
10.15.5 Transmit Pattern Generation.............................................................................................................. 196
10.16LINE INTERFACE UNIT (LIU).........................................................................................................197
10.16.1 General Description ........................................................................................................................... 197
10.16.2 Features............................................................................................................................................. 197
10.16.3 Detailed Description........................................................................................................................... 198
10.16.4 Transmitter......................................................................................................................................... 198
10.16.5 Receiver............................................................................................................................................. 199
11 OVERALL REGISTER MAP
12 REGISTER MAPS AND DESCRIPTIONS
202
204
12.1 REGISTERS BIT MAPS .................................................................................................................204
12.1.1 Global Register Bit Map ..................................................................................................................... 204
12.1.2 HDLC Register Bit Map...................................................................................................................... 207
12.1.3 T3 Register Bit Map ........................................................................................................................... 209
12.1.4 E3 G.751 Register Bit Map ................................................................................................................ 210
12.1.5 E3 G.832 Register Bit Map ................................................................................................................ 211
12.1.6 Clear-Channel Register Bit Map ........................................................................................................ 212
12.1.7 Fractional Register Bit Map................................................................................................................ 212
12.1.8 Transmit Cell Processor Bit Map ....................................................................................................... 215
12.1.9 Transmit Packet Processor Bit Map................................................................................................... 216
12.2 GLOBAL REGISTERS....................................................................................................................219
12.2.1 Register Bit Descriptions.................................................................................................................... 219
12.3 UTOPIA/POS-PHY SYSTEM INTERFACE.....................................................................................227
12.3.1 Transmit System Interface................................................................................................................. 227
12.3.2 Receive System Interface Register Map............................................................................................ 229
12.4 PER-PORT COMMON ...................................................................................................................231
12.4.1 Per-Port Common Register Map........................................................................................................ 231
12.4.2 Per-Port Common Register Bit Descriptions......................................................................................231
12.5 BERT.........................................................................................................................................242
12.5.1 BERT Register Map ........................................................................................................................... 242
12.5.2 BERT Register Bit Descriptions......................................................................................................... 242
12.6 B3ZS/HDB3 LINE ENCODER/DECODER.......................................................................................251
12.6.1 Transmit Side Line Encoder/Decoder Register Map ......................................................................... 251
12.6.2 Receive Side Line Encoder/Decoder Register Map .......................................................................... 252
12.7 HDLC.........................................................................................................................................256
12.7.1 HDLC Transmit Side Register Map.................................................................................................... 256
12.7.2 HDLC Receive Side Register Map..................................................................................................... 260
12.8 FEAC CONTROLLER ...................................................................................................................264
12.8.1 FEAC Transmit Side Register Map.................................................................................................... 264
12.8.2 FEAC Receive Side Register Map..................................................................................................... 267
12.9 TRAIL TRACE ..............................................................................................................................270
12.9.1 Trail Trace Transmit Side................................................................................................................... 270
12.9.2 Trail Trace Receive Side Register Map ............................................................................................. 272
12.10DS3/E3 FRAMER ........................................................................................................................276
12.10.1 Transmit DS3 ..................................................................................................................................... 276
12.10.2 Receive DS3 Register Map................................................................................................................ 279
12.10.3 Transmit G.751 E3............................................................................................................................. 289
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