Datasheet > DS31408GN

DS31408GN

更新时间： 2024-02-28 04:44:39

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
6页	219K
描述
8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock

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技术参数
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DS31408GN 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	BGA,
针数：	256	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	1.76
JESD-30 代码：	S-PBGA-B256	功能数量：	1
端子数量：	256	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	BALL	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

DS31408GN 数据手册

ABRIDGED DATA SHEET

DS31408

Detailed Features

Input Clock Features



Eight input clocks, differential or CMOS/TTL signal format

Input clocks can be any frequency from 2kHz up to 750MHz

Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3

Per-input fractional scaling (i.e., multiplying by ND where N is a 16-bit integer and D is a 32-bit integer

and N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)

Special mode allows locking to 1Hz input clocks

All inputs constantly monitored by programmable activity monitors and frequency monitors

Fast activity monitor can disqualify the selected reference after a few missing clock cycles

Frequency measurement and frequency monitor thresholds with 0.2ppm resolution

Three optional 2/4/8kHz frame-sync inputs



DPLL Features



Very high-resolution DPLL architecture

Sophisticated state machine automatically transitions between free-run, locked, and holdover states

Revertive or nonrevertive reference selection algorithm

Programmable bandwidth from 0.5mHz to 400Hz

Separately configurable acquisition bandwidth and locked bandwidth

Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20

Multiple phase detectors: phase/frequency and multicycle

Phase/frequency locking (360 capture) or nearest edge phase locking (180 capture)

Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time

Phase build-out in response to reference switching for true hitless switching

Less than 1 ns output clock phase transient during phase build-out

Output phase adjustment up to 200ns in 6ps steps with respect to selected input reference

High-resolution frequency and phase measurement

Holdover frequency averaging over 1-second, 5.8-minute, and 93.2-minute intervals

Fast detection of input clock failure and transition to holdover mode

Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks

Digital Frequency Synthesizer Features



Seven independently programmable DFS blocks

Each DFS can slave to either of the DPLLs

Each DFS can synthesize any 2kHz multiple up to 77.76MHz

Per-DFS phase adjust (1/256UI steps)

Approximately 40ps RMS output jitter

Output APLL Features



Simultaneously produce three high-frequency, low-jitter, rates from the same reference clock, e.g.,

622.08MHz for SONET, 255/237*622.08MHz for OTU2, and156.25MHz for 10GE

Standard telecom output frequencies include 622.08MHz, 155.52MHz, and 19.44MHz for SONET/SDH

and 156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet

Very high-resolution fractional scaling (i.e., noninteger multiplication)

Less than 1ps RMS output jitter



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与DS31408GN相关器件

型号	品牌	描述	获取价格	数据表
DS31408GN+	MAXIM	8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock	获取价格
DS3141	MAXIM	Single/Dual/Triple/Quad DS3/E3 Framers	获取价格
DS3141	DALLAS	Single/Dual/Triple/Quad DS3/E3 Framers	获取价格
DS3141+	MAXIM	暂无描述	获取价格
DS31412	MAXIM	6-/8-/12-Channel DS3/E3 Framers	获取价格
DS31412N	MAXIM	6-/8-/12-Channel DS3/E3 Framers	获取价格

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