Datasheet > DS31408_1107

DS31408_1107

更新时间： 2022-10-27 16:37:04

品牌	Logo	应用领域
美信 - MAXIM		时钟
页数	文件大小	规格书
6页	83K
描述
8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock

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数据手册

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DS31408_1107 数据手册

ABRIDGED DATA SHEET

DS31408

Block Diagram

DS31408

1588 out1

FSYNC

SYNC1

SYNC2

SYNC3

1588 out2

MFSYNC

PLL Bypass

DFS Muxes

Divider Muxes

Dif Muxes

OC1

DPLL1

DFS 1

Divider 1

IC1 POS/NEG

IC2 POS/NEG

IC3 POS/NEG

IC4 POS/NEG

IC5 POS/NEG

IC6 POS/NEG

IC7 POS/NEG

IC8 POS/NEG

Filtering, Holdover,

Hitless Switching, PBO,

Frequency Conversion,

Manual Phase Adjust

OC1POS/NEG

APLL1

APLL2

APLL3

lowest jitter path

OC2

DFS 2

DFS 3

Divider 2

Input Clock

Block

OC2POS/NEG

lowest jitter path

OC3

Divider 3

Frequency Scaler,

Activity Monitor,

Freq. Monitor,

Optional Inversion

(per input clock)

OC3POS/NEG

lowest jitter path

OC4

Divider 4

Divider 5

Divider 6

Divider 7

DFS 4

DFS 5

DFS 6

DFS 7

OC4POS/NEG

DPLL2

identical to DPLL1

OC5

OC5POS/NEG

OC6

Clock

Selector

status

OC6POS/NEG

OC7

OC7POS/NEG

MCLK

ICx

OCx

SYNCx

ICx

OCx

JTRST

JTMS

JTCLK

JTDI

clkin

tain

out1

out2

Master

Clock

APLL

1588

Time

Engine

Microprocessor Port

(SPI Serial)

and HW Control and Status Pins

JTAG

JTDO

MCLKOSC

Local Oscillator

TCXO or OCXO

1 2 345 6

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