Datasheet > DS3112N+W

DS3112N+W

更新时间： 2024-02-22 17:44:55

品牌	Logo	应用领域
美信 - MAXIM		电信电信集成电路
页数	文件大小	规格书
133页	1033K
描述
Framer, CMOS, PBGA256, 27 X 27 MM, 2.13 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-256

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DS3112N+W 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	27 X 27 MM, 2.13 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-256	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.62	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e3	长度：	27 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	256	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	2.34 mm
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	FRAMER
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	27 mm	Base Number Matches：	1

DS3112N+W 数据手册

DS3112

1 DETAILED DESCRIPTION

The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer.

When the device is used as a multiplexer, it can be operated in one of three modes:

M13—Multiplex 28 T1 lines into a T3 data stream

E13—Multiplex 16 E1 lines into an E3 data stream

G.747—Multiplex 21 E1 lines into a T3 data stream

See Figure 1-1, Figure 1-2, and Figure 1-3 for block diagrams of these three modes. In each of the block

diagrams, the receive section is at the bottom and the transmit section is at the top. The receive path is

defined as incoming T3/E3 data and the transmit path is defined as outgoing T3/E3 data. When the device

is operated solely as a T3 or E3 framer, the multiplexer portion of the device is disabled and the raw

T3/E3 payload will be output at the FRD output and input at the FTD input. See Figure 1-1 and

Figure 1-2 for details.

In the receive path, raw T3/E3 data is clocked into the device (either in a bipolar or unipolar fashion) with

the HRCLK at the HRPOS and HRNEG inputs. The data is then framed by the T3/E3 framer and passed

through the two-step demultiplexing process to yield the resultant T1 and E1 data streams, which are

output at the LRCLK and LRDAT outputs. In the transmit path, the reverse occurs. The T1 and E1 data

streams are input to the device at the LTCLK and LTDAT inputs. The device will sample these inputs

and then multiplex the T1 and E1 data streams through a two-step multiplexing process to yield the

resultant T3 or E3 data stream. Then this data stream is passed through the T3/E3 formatter to have the

framing overhead added, and the final data stream to be transmitted is output at the HTPOS and HTNEG

outputs using the HTCLK output.

The DS3112 has been designed to meet all of the latest telecommunications standards. Section 1.1 lists all

of the applicable standards for the device.

The TEMPE device has a number of advanced features such as:

•

The ability to drop and insert up to two T1 or E1 ports

An on-board HDLC controller with 256-byte buffers

An on-board Bit Error Rate Tester (BERT)

Advanced diagnostics to create and detect many different types of errors

See Section 1.2 for a complete list of main features within the device.

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