DS26S10J

更新时间： 2024-11-23 13:07:27

品牌	Logo	应用领域
美国国家半导体 - NSC		总线收发器
页数	文件大小	规格书
7页	158K
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DS26S10J 数据手册

May 1999

DS26S10

Quad Bus Transceiver

The DS26S10 features advanced Schottky processing to

minimize propagation delay. The device package also has 2

ground pins to improve ground current handling and allow

close decoupling between V_CCand ground at the package.

Both GND 1 and GND 2 should be tied to the ground bus ex-

ternal to the device package.

General Description

The DS26S10 is a quad Bus Transceiver consisting of 4 high

speed bus drivers with open-collector outputs capable of

sinking 100 mA at 0.8V and 4 high speed bus receivers.

Each driver output is connected internally to the high speed

bus receiver in addition to being connected to the package

pin. The receiver has a Schottky TTL output capable of driv-

ing 10 Schottky TTL unit loads.

Features

n Input to bus is inverting on DS26S10

n Quad high speed open-collector bus transceivers

n Driver outputs can sink 100 mA at 0.8V maximum

n Advanced Schottky processing

An active low enable gate controls the 4 drivers so that out-

puts of different device drivers can be connected together for

party-line operation.

The bus output high-drive capability in the low state allows

party-line operation with a line impedance as low as 100Ω.

The line can be terminated at both ends, and still give con-

siderable noise margin at the receiver. The receiver typical

switching point is 2V.

n PNP inputs to reduce input loading

Logic Diagrams

DS2610

DS005802-1

DS005802

www.national.com

12 3 4 5 6 7

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