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DS250DF230RTVT

更新时间: 2024-11-24 02:50:55
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德州仪器 - TI /
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描述
DS250DF230 25-Gbps Multi-Rate 2-Channel Retimer

DS250DF230RTVT 数据手册

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DS250DF230  
SNLS590B AUGUST 2018REVISED OCTOBER 2019  
DS250DF230 25-Gbps Multi-Rate 2-Channel Retimer  
1 Features  
2 Applications  
1
Dual-channel multi-rate retimer with integrated  
Jitter cleaning for front-port optical interface in  
signal conditioning  
wireless and wired systems  
Backplane/mid-plane reach extension  
Active cable assemblies  
All channels lock independently from 19.6 to 25.8  
Gbps (including sub-rates, such as 12.16512  
Gbps, 9.8304 Gbps, 6.144 Gbps, and more)  
802.3bj 100GbE, InfiniBand EDR, and OIF-CEI-  
25G-LR/MR/SR/VSR electrical interfaces  
Ultra-low latency: <500 ps Typical for 25.78125-  
Gbps data rate  
SFP28, QSFP28, CFP2/CFP4, CDFP  
Adaptive continuous time linear equalizer (CTLE)  
Continuous adaptive decision feedback equalizer  
(DFE), capable of compensating large channel  
loss variation over temperature  
3 Description  
The DS250DF230 is a dual-channel multi-rate retimer  
with integrated signal conditioning. The device is  
used to extend the reach and robustness of long,  
lossy, crosstalk-impaired high-speed serial links and  
while achieving a bit error rate (BER) of 10–15 or less.  
Combined equalization supporting 35-dB channel  
loss at 12.9 GHz  
On-chip eye-opening monitor (EOM), PRBS  
pattern checker and generator  
Each channel of the DS250DF230 independently  
locks to serial data rates in a continuous range from  
19.6 Gbps to 25.8 Gbps or to any supported sub-rate  
(÷2 and ÷4), including key data rates such as  
12.16512 Gbps, 9.8304 Gbps, 6.144 Gbps.  
Low-jitter transmitter with 3-Tap FIR filter  
Integrated 2×2 cross-point  
Recovered clock available for system clock  
synchronization applications on channel 0  
Device Information(1)  
Single power supply, no low-jitter reference clock  
required  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
DS250DF230  
NFBGA (36)  
5.00 mm × 5.00 mm  
Wide stay-in-lock temperature range  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Simplified Schematic  
RX0P  
RX0N  
TX0P  
TX0N  
CDR  
X
RX  
TX  
RX1P  
RX1N  
TX1P  
TX1N  
CDR  
RX  
TX  
2.5V or 3.3V  
VDD  
SMBus  
Slave mode  
1 kΩ  
To other open-drain  
interrupt pins  
EN_SMB  
INT_N  
SDA(1)  
TEST0 /RCK0  
THR /TEST1  
To system  
SMBus  
SDC(1)  
Address straps  
ADDR0  
(pull-up, pull-  
ADDR1  
down, or float)  
30.72 MHz or 25 MHz  
To next device‘s  
CAL_CLK_IN  
CAL_CLK_IN  
READ_EN_N  
CAL_CLK_OUT  
ALL_DONE_N  
SMBus Slave  
mode  
2.5 V  
Float for SMBus Slave  
mode, or connect to next  
device‘s READ_EN_N for  
SMBus Master mode  
GND  
VDD  
0.01 F  
(2x)  
0.1 F  
(2x)  
(1) SMBus signals need to be pulled up elsewhere in the system.  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 

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