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DS2480BS PDF预览

DS2480BS

更新时间: 2024-02-12 08:21:08
品牌 Logo 应用领域
达拉斯 - DALLAS 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
30页 410K
描述
Serial 1-Wire Line Driver with Load Sensor

DS2480BS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
风险等级:5.87JESD-30 代码:R-PDSO-G8
JESD-609代码:e0湿度敏感等级:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
子类别:Serial IO/Communication Controllers标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL

DS2480BS 数据手册

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DS2480B  
into eight 1-Wire time slots, thereby increasing the data throughput significantly. In addition, the  
DS2480B can be set to communicate at four different data rates, including 115.2 kbps, 57.6 kbps and 19.2  
kbps with 9.6 kbps being the power-on default. Command codes received from the host’s crystal  
controlled UART serve as a reference to continuously calibrate the on-chip timing generator. The  
DS2480B uses a unique protocol that merges data and control information without requiring control pins.  
This approach maintains compatibility to off-the-shelf serial to wireless converters, allowing easy  
realization of 1-Wire media jumpers. The various control functions of the DS2480B are optimized for  
MicroLAN 1-Wire networks and support the special needs of all current 1-Wire devices including the  
crypto iButton, EPROM-based Add-Only Memories, EEPROM devices and 1-Wire Thermometers.  
DETAILED PIN DESCRIPTION  
PIN SYMBOL DESCRIPTION  
1
2
GND  
1-W  
Ground Pin: common ground reference and ground return for 1-Wire bus  
1–Wire Input/Output Pin: 1–Wire bus with slew–rate–controlled pulldown,  
active pullup, ability to switch in VPP to program EPROM, and ability to switch  
in VDD through a low–impedance path to program EEPROM, perform a  
temperature conversion or operate the crypto iButton.  
3
4
NC  
VDD  
No Connection Pin.  
Power Input Pin: power supply for the chip and 1–Wire pullup voltage, 5V  
±10%, must always be lower than VPP. VDD should be derived from VPP by a  
separate voltage regulator. If EPROM programming is not required feed VDD  
from VPP through a Schottky diode to get a 0.3V drop at VDD.  
EPROM Programming Voltage: 12V supply input for EPROM programming.  
If EPROM programming is not required, connect this pin directly to the system’s  
5V supply.  
5
VPP  
6
7
8
POL  
TXD  
RXD  
RXD/TXD Polarity Select: RXD/TXD polarity select; tied to GND for RS232  
(12V or 5V) connection; tied to VDD for direct connection to UART chip.  
Serial Data from UART: data input from host (inverted or true); maximum  
voltage swing –0.3V to VDD + 0.3V; for logic thresholds see DC specifications.  
Serial Data to UART: signal output to host; push–pull driver with CMOS  
compatible levels; for true ±12V RS232 systems an external level translator must  
be provided.  
OVERVIEW  
The DS2480B directly interfaces a 5V serial communication port with its lines TXD (transmit) and RXD  
(receive) to a 1–Wire bus. In addition the device performs a speed conversion allowing the data rate at the  
communication port to be different from the 1–Wire data rate. Several parameters relating to the 1–Wire  
port and its timing as well as the communication speed at both the port and the 1–Wire bus are  
configurable. The circuit to achieve these functions is outlined in Figure 1, Block Diagram.  
The device gets its input data from the serial communication port of the host computer through pin TXD.  
For compatibility with active–high as well as active–low systems, the incoming signal can be inverted by  
means of the polarity input POL. The polarity chosen by hard–wiring the logic level of this pin is also  
valid for the output pin RXD. If for minimizing the interface hardware an asymmetry between RXD and  
TXD is desired, this can be achieved by setting the most significant bit of the Speed Control parameter to  
a 1 (see Configuration Parameter Value Codes). With the MS bit of the speed control set to 1, the polarity  
at TXD is still selected by the logic level at POL, but the polarity at RXD will be the opposite of what the  
logic level at POL specifies.  
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