ABRIDGED DATA SHEET
DS2476
DeepCover Secure Coprocessor
Electrical Characteristics (continued)
(T = -40°C to +85°C.) (Note 1)
A
Note 1: Limits are 100% production tested at T = +25°C and/or T = +85°C. Limits over the operating temperature range and
A
A
relevant supply voltage range are guaranteed by design and characterization. Typical values at +25°C.
Note 2: Operating current continuously reading memory at 400kHz with < 25ns rise and fall times on SDA and SCL.
Note 3: Average current drawn from V during EEPROM read, EEPROM write, RNG calculation, SHA-256 calculation, or ECDSA calculation.
CC
Note 4: Write-cycle endurance is tested in compliance with JESD47H.
Note 5: Data retention is rested in compliance with JESD47H.
2
Note 6: All I C timing values are referred to V
and V
levels.
IH(MIN)
IL(MAX)
Note 7: Guaranteed by design and/or characterization only. Not production tested.
Note 8: I/O pins of the DS2476B do not obstruct the SDA and SCL lines if V
Note 9: System requirement.
is switched off.
CC
Note 10: t
min = t
max + t
max + t
min, where t
is rise or fall time. For the DS2476, t
max = 300ns;
LOW
HD:DAT
EDGE
SU:DAT
EDGE
EDGE
for the DS2476B, t
max = 200ns. Values greater than these can be accommodated by extending t
accordingly.
EDGE
LOW
Note 11: The DS2476 provides a hold time of at least 100ns for the SDA signal (referred to the V
of the SCL signal) to bridge
IH(MIN)
the undefined region of the falling edge of SCL. The master can provide a hold time of 0ns when writing to the device.
2
2
Note 12: The DS2476 can be used in a standard-mode I C bus system, but the requirement t
≥ 250ns must then be met (I C
SU:DAT
bus specification Rev. 03, 19 June 2007).
Note 13: C = total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending
B
2
on the actual operating voltage and frequency of the application (I C bus specification Rev. 03, 19 June 2007).
2
Note 14: I C communication should not take place for max t
time following a power-on reset.
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