ABRIDGED DATA SHEET
DS2465
SHA-256 Coprocessor with 1-Wire Master Function
LAST BIT OF 1-Wire WRITE BYTE, 1-Wire READ BYTE, OR 1-Wire SINGLE BIT FUNCTION
V
CC
WRITE-ONE CASE
V
IAPO
0V
WRITE-ZERO CASE
NEXT
TIME SLOT
t
SLOT
DS2465 RESISTIVE PULLUP
DS2465 PULLDOWN
DS2465 STRONG PULLUP
Figure 3. Low-Impedance Pullup Timing
Bit 1: 1-Wire Power-Down (PDN). The PDN bit is used to remove power from the 1-Wire port, e.g., to force a 1-Wire
slave to perform a power-on reset. PDN interacts with the sleep mode, which is controlled by the SLPZ pin (Table 4).
The default state of PDN is 0, enabling normal operation. When PDN is changed to 1, no 1-Wire communication is
possible. To end the 1-Wire power-down state, the PDN bit needs to be changed to 0. To exit the DS2465 from sleep
mode, change the SLPZ pin state from 0 to 1. This forces the DS2465 to perform a power-on reset and clears PDN to
0 for normal operation.
Table ꢁ. Interaction of PDN and SLPZ
SLPZ PIN IS AT LOGIC ꢀ
SLPZ PIN IS AT LOGIC 1
is connected;
• R
WPU
PDN is ꢀ
PDN is 1
IO is at V , keeping the slaves powered.
• The DS2465 is powered up (normal operation).
CC
• R
is disconnected;
WPU
IO is at 0V, causing the slaves to lose power.
• The DS2465 is powered down (sleep mode).
• R
is disconnected;
WPU
IO is at 0V, causing the slaves to lose power.
• The DS2465 is powered up.
Bit ꢀ: Active Pullup (APU). The APU bit controls whether an active pullup (low impedance transistor) or a passive
pullup (R resistor) is used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor
WPU
mode). Enabling active pullup is generally recommended for best 1-Wire performance. The active pullup does not apply
to the rising edge of a recovery after a short on the 1-Wire line. If enabled, a fixed-duration active pullup (nominally
2.5Fs standard speed, 0.5Fs overdrive speed) also applies in a reset/presence detect cycle on the rising edges after
t
and after t
.
RSTL
PDL
The circuit that controls rising edges (Figure 4) operates as follows: At t , the pulldown (from DS2465 or 1-Wire slave)
1
ends. From this point on the 1-Wire line is pulled high through R
internal to the DS2465. V
and the capacitive load
WPU
CC
of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues,
as represented by the solid line. With active pullup enabled (APU = 1), and when at t the voltage has reached the
2
V
threshold, the DS2465 activates a low-impedance pullup transistor, as represented by the dashed line. The active
IAPO
pullup remains active until the end of the time slot (t ), after which the resistive pullup continues. The shortest duration
3
of the active pullup is t
in a write-zero time slot and the longest duration is t
+ t
- t
in a write-one time
REC0
W0L
REC0 W1L
slot. In a read data time slot, the active pullup duration is slave dependent. See the strong pullup (SPU) section for a
way to keep the pullup transistor conducting beyond t .
3
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