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DS2176N PDF预览

DS2176N

更新时间: 2024-01-06 20:36:35
品牌 Logo 应用领域
达拉斯 - DALLAS 数字传输支持电信集成电路电信电路光电二极管PC
页数 文件大小 规格书
15页 297K
描述
T1 Receive Buffer

DS2176N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-28针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.32
运营商类型:CEPT PCM-30/E-1运营商类型(2):T-1(DS1)
数据速率:2048 MbpsJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Digital Transmission Interfaces最大压摆率:0.01 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:ELASTIC BUFFER
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.505 mmBase Number Matches:1

DS2176N 数据手册

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DS2176  
passed through the receive buffer and presented at SSER immediately after the rising edge of the system  
side frame sync. The F–bit is dropped in 2.048 MHz applications and the MSB of channel 1 appears at  
SSER one bit period after a rising edge at SFSYNC. SSER is forced to 1 in all channels greater than 24.  
See Figures 3 and 4.  
In 2.048 MHz applications (SCLKSEL=1), the PCM buffer control logic establishes slip criteria different  
from that used in 1.544 MHz applications to compensate for the faster system-side read frequency.  
PARALLEL COMPATIBILITY  
The DS2176 is compatible with parallel and serial back-planes. Channel 1 data appears at SSER after a  
rising edge at SFSYNC as shown in Figures 3 and 4 (serial applications, S/ P =1). The device utilizes a  
look–ahead circuit in parallel applications (S/ P =0). Data is output 8 clocks earlier, allowing the user to  
convert parallel data eternally.  
SYSTEM MULTIFRAME BOUNDARY TIMING (SYSCLK = 1.544 MHz) Figure 3  
5 of 15  

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