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DS2165Q/T&R PDF预览

DS2165Q/T&R

更新时间: 2024-02-03 20:24:59
品牌 Logo 应用领域
美信 - MAXIM PC电信电信集成电路
页数 文件大小 规格书
17页 342K
描述
ADPCM Codec, A/MU-Law, 1-Func, CMOS, PQCC28, PLASTIC, LCC-28

DS2165Q/T&R 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
压伸定律:A/MU-LAW滤波器:NO
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.505 mm湿度敏感等级:1
功能数量:1端子数量:28
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
认证状态:Not Qualified座面最大高度:4.57 mm
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:ADPCM CODEC
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11.505 mmBase Number Matches:1

DS2165Q/T&R 数据手册

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DS2165Q  
HARDWARE MODE  
The hardware mode is intended for applications that do not have an external controller available or do not  
require the extended features offered by the serial port. Connecting the SPS pin to VSS disables the serial  
port, clears all internal register bits, and maps the IPD, U/
A
, and CP/EX bits for both channels to external  
bits (Table 3). In the hardware mode, both the input and output time slots default to time slot 0.  
Table 3. HARDWARE MODE  
PIN  
REGISTER LOCATION  
FUNCTION  
#
NAME  
Channel X Coding Configuration  
0 = Expand  
CP/EX  
(Channel X)  
AS0/AS1/AS2  
(Channel X and Y)  
6
A0  
1 = Compress  
7
8
A1  
A2  
Algorithm Select (Table 4)  
Channel X Data Format  
0 = A-law  
U/ A  
(Channel X)  
1 = -law  
Channel Y Coding Configuration  
0 = Expand  
CP/EX  
(Channel Y)  
AS0/AS1/AS2  
(Channel X and Y)  
9
A3  
A4  
A5  
1 = Compress  
10  
11  
Algorithm Select (Table 4)  
Channel Y Data Format  
0 = A-law  
U/ A  
(Channel Y)  
1 = -law  
Channel Y Idle Select  
0 = Channel Active  
1 = Channel Idle  
Channel X Idle Select  
0 = Channel Active  
1 = Channel Idle  
IPD  
22  
23  
SDI  
(Channel Y)  
IPD  
(Channel X)  
CS  
NOTES:  
1) SCLK must be connected to VSS when the hardware mode is selected.  
2) When both channels are idled, power consumption is significantly reduced.  
3) The NIL powers up within 800ms after either channel is returned to active from an idle state.  
9 of 17  

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